PIC18F242 datasheet(227/332 Pages) MICROCHIP

227 / 332 page

DS39564C-page 225

PIC18FXX2

BTG

Bit Toggle f

Syntax:

[

label ] BTG f,b[,a]

Operands:

≤ f ≤ 255

≤ b ≤ 7

∈ [0,1]

Operation:

(f<b>)

→ f<b>

Status Affected:

None

Encoding:

0111

bbba

ffff

Description:

Bit 'b' in data memory location 'f' is

inverted. If ‘a’ is 0, the Access Bank

will be selected, overriding the BSR

value. If ‘a’ = 1, then the bank will be

selected as per the BSR value

(default).

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write

Example:

BTG

PORTC,

4, 0

Before Instruction:

PORTC

0111 0101

[0x75]

After Instruction:

PORTC

0110 0101

[0x65]

BOV

Branch if Overflow

Syntax:

[

label ] BOV

Operands:

-128

≤ n ≤ 127

Operation:

if overflow bit is ’1’

(PC) + 2 + 2n

→ PC

Status Affected:

None

Encoding:

1110

0100

nnnn

Description:

If the Overflow bit is ’1’, then the

program will branch.

The 2’s complement number ’2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

Words:

Cycles:

1(2)

Q Cycle Activity:

If Jump:

Decode

Read literal

'n'

Process

Data

Write to PC

operation

If No Jump:

Decode

Read literal

'n'

Process

Data

operation

Example:

HERE

BOV

Jump

Before Instruction

address (HERE)

After Instruction

If Overflow

address (Jump)

If Overflow

address (HERE+2)

PIC18F242 bảng dữ liệu(PDF) 227 Page - Microchip Technology

PIC18F242 bảng dữ liệu(HTML) 227 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL