IXP2400 datasheet(21/126 Pages) INTEL

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Intel® IXP2400 Network Processor

Datasheet

2.8

XPI Unit

2.8.1

GPIO

The IXP2400 contains eight General-Purpose IO (GPIO) pins. These can be programmed as either

input or output, and can be used for slow-speed IO, such as LEDs or input switches. They can also

be used as interrupts to the Intel XScale core, or to clock the programmable timers.

2.8.2

Serial Port

The IXP2400 contains a standard RS-232–compatible universal asynchronous receiver/transmitter

(UART), which can be used for communication with a debugger or maintenance console. Modem

controls are not supported; if they are needed, GPIO pins can be used for that purpose.

The UART performs serial-to-parallel conversion on data characters received from a peripheral

device and parallel-to-serial conversion on data characters received from the processor. The

processor can read the complete status of the UART at any time during operation. Available status

information includes the type and condition of the transfer operations being performed by the

UART and any error conditions (parity, overrun, framing or break interrupt).

The serial ports can operate in either FIFO or non-FIFO mode. In FIFO mode, a 64-byte transmit

FIFO holds data from the processor to be transmitted on the serial link and a 64-byte receive FIFO

buffers data from the serial link until read by the processor.

The UART includes a programmable baud rate generator that is capable of dividing the internal

clock input (APB_CLK, running at 50 MHz) by divisors of 1 to 216 - 1, and produces a 16x clock to

drive the internal transmitter logic. It also drives the receive logic. The UART can be operated in

polled or in interrupt-driven mode as selected by software.

The UART has two clocks: The clock from the baud rate generator for transmit and receive

operation, and the clock from the XPI unit for register reads and writes.

2.8.3

SlowPort

The SlowPort is an external interface to the IXP2400 and is used for Flash memory access and 8-,

16-, or 32-bit asynchronous device access. It allows the Intel XScale core to do read/ write data

transfers to these slave devices.

The address bus and data bus are multiplexed to reduce the pin count. In addition, the address bus is

also compressed from A[24:0] down to A[7:0] and shifted out with three clock cycles in Mode 0,

and four clock cycles in Mode 1–4. Therefore, an external set of buffers is needed to latch the

address. Two chip selects are provided. Several modes of configurations are supported to connect

with the microprocessor control port of various framers or MAC devices. See Figure 8 for an

example configuration (note that the ACK signal is optional).

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