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AV0732E bảng dữ liệu(PDF) 3 Page - Aplus Intergrated Circuits |
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AV0732E bảng dữ liệu(HTML) 3 Page - Aplus Intergrated Circuits |
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3 / 10 page ![]() AVXX32E -A SERIES Pin Description Pin Name I/O Description VDD Power Positive power supply TEST In Test enable pad, high-active, pull-low OSC In With resister connected to VDD for system clock generating OKY In Trigger input, active-high, with internal pull_low resistor. Can define as sequential key or random key. TG0, TG1 In Trigger input, active-high with internal pull_low resistor. In Trigger input, active-high TG3_OPC Out Status output OPB Out Status output OPA Out Status output PWM1, PWM2 Out Voltage output to drive speaker or buzzer VSS Power Negative power supply Absolute Maximum Rating Symbol Rating Unit VDD~VSS -0.5 ~ +0.5 V VIN (for input) VSS-0.3 < VIN < VDD+0.3 V VOUT (for all outputs) VSS < VOUT < VDD V T (operating) -10 ~ +60 T (storage) -55 ~ +125 DC Characteristics Symbol Parameter Min Typ. Max Unit Condition VDD Operating Voltage 2.4 3.0 5.0 V Isb Standby 1 A VDD=3.0V, I/O open Iop Supply Current Operating 400 A VDD=3.0V, No loading IOL OPA, OPB source Current –20 mA VDD=3.0V, VIP=2.7V Ioh OPA, OPB sink Current 20 mA VDD=3.0V, VOP=0.3V d F/F Frequency Variation by diff. lot 10 % VDD=4.5V fOSC =384kHz Function Diagram 1. OPA/B/C (1:0) are the output options. Output Option 0(00) 1(01) 2(10) 3(11) Status BH DL SH DH OPA LED +Fast +Slow Dy07 OFF Status BH DL SH DH OPB LED -Fast -Slow Dy09 ON Status BH DL BL DH OPC LED +Fast +Slow ON OFF Status output mode: SH: Single pulse output, hi-level output Preliminary 9-2 Ver. 0.1 BH: Busy output, hi-level output |
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