MFRC53001TSLASH0FE datasheet(2/116 Pages) PHILIPS

2 / 116 page

MFRC530_33

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Product data sheet

PUBLIC

Rev. 3.3 — 6 July 2010

057433

2 of 115

NXP Semiconductors

MFRC530

ISO/IEC 14443 A Reader IC

Features and benefits

3.1 General

Highly integrated analog circuitry for demodulating and decoding card response

Buffered output drivers enable antenna connection using the minimum of external

components

Proximity operating distance up to 100 mm

Supports the ISO/IEC 14443 A standard, parts 1 to 4

Supports MIFARE dual-interface card ICs and MIFARE Classic protocol

Crypto1 and secure non-volatile internal key memory

Pin-compatible with the CLRC632, MFRC500, MFRC531 and the SLRC400

Parallel microprocessor interface with internal address latch and IRQ line

Flexible interrupt handling

Automatic detection of parallel microprocessor interface type

64-byte send and receive FIFO buffer

Hard reset with low power function

Software triggered Power-down mode

Programmable timer

Unique serial number

User programmable start-up configuration

Bit-oriented and byte oriented framing

Independent power supply pins for analog, digital and transmitter modules

Internal oscillator buffer optimized for low phase jitter enables 13.56 MHz quartz

connection

Clock frequency filtering

3.3 V to 5 V operation for transmitter in short range and proximity applications

3.3 V or 5 V operation for the digital module

Applications

Electronic payment systems

Identification systems

Access control systems

Subscriber services

Banking systems

Digital content systems

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