3

Exposed

Thermal Pad

9

10

11

12

8

7

6

5

4

2

1

16

15

14

13

PVIN

PVIN

AVIN

SS/TR

SW

SW

SW

PG

TLV62150, TLV62150A

SLVSB71B – FEBRUARY 2012 – REVISED JUNE 2013

www.ti.com

DEVICE INFORMATION

RGT PACKAGE

(TOP VIEW)

Terminal Functions

I/O

DESCRIPTION

NAME

NO.

SW

1,2,3

O

Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and

output capacitor.

PG

4

O

Output power good (High = VOUT ready, Low = VOUT below nominal regulation) ; open drain (requires

pull-up resistor; goes high impedance, when device is switched off)

FB

5

I

Voltage feedback. Connect resistive voltage divider to this pin.

AGND

6

Analog Ground. Must be connected directly to the Exposed Thermal Pad and common ground plane.

FSW

7

I

Switching Frequency Select (Low

DEF

8

I

Soft-Start / Tracking Pin. An external capacitor connected to this pin sets the internal voltage reference rise

SS/TR

9

I

time. It can be used for tracking and sequencing.

AVIN

10

I

Supply voltage for control circuitry. Connect to same source as PVIN.

PVIN

11,12

I

Supply voltage for power stage. Connect to same source as AVIN.

EN

13

I

VOS

14

I

Output voltage sense pin and connection for the control loop circuitry.

PGND

15,16

Power ground. Must be connected directly to the Exposed Thermal Pad and common ground plane.

Exposed

Thermal Pad

achieve appropriate power dissipation and mechanical reliability.

(1)

For more information about connecting pins, see DETAILED DESCRIPTION and APPLICATION INFORMATION sections.

(2)

Connect FSW to VOUT or PG in this case.

(3)

An internal pull-down resistor keeps logic level low, if pin is floating.

(4)

See Figure 38.

4

Submit Documentation Feedback

Copyright © 2012–2013, Texas Instruments Incorporated

Product Folder Links: TLV62150 TLV62150A