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STM32F373CC bảng dữ liệu(PDF) 23 Page - STMicroelectronics |
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STM32F373CC bảng dữ liệu(HTML) 23 Page - STMicroelectronics |
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23 / 131 page  DocID022691 Rev 4 23/131 STM32F37xxx Functional overview 47 3.17.3 Independent watchdog (IWDG) The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. 3.17.4 System window watchdog (WWDG) The system window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the APB1 clock (PCLK1) derived from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.17.5 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: • A 24-bit down counter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0 • Programmable clock source 3.18 Real-time clock (RTC) and backup registers The RTC and the backup registers are supplied through a switch that takes power either from VDD supply when present or through the VBAT pin. The backup registers are thirty two 32-bit registers used to store 128 bytes of user application data. They are not reset by a system or power reset, and they are not reset when the device wakes up from the Standby mode. |
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