STM32F217VG datasheet(35/175 Pages) STMICROELECTRONICS

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STM32F21xxx

Functional overview

174

3.31.1

Cryptographic acceleration

The STM32F215xx and STM32F217xx devices embed a cryptographic accelerator. This

cryptographic accelerator provides a set of hardware acceleration for the advanced

cryptographic algorithms usually needed to provide confidentiality, authentication, data

integrity and non repudiation when exchanging messages with a peer.

•

These algorithms consists of:

Encryption/Decryption

–

DES/TDES (data encryption standard/triple data encryption standard): ECB

(electronic codebook) and CBC (cipher block chaining) chaining algorithms, 64-,

128- or 192-bit key

–

AES (advanced encryption standard): ECB, CBC and CTR (counter mode)

chaining algorithms, 128, 192 or 256-bit key

Universal hash

–

SHA-1 (secure hash algorithm)

–MD5

•

It also provides a true random number generator that deliver 32-bit random numbers

produced by an integrated analog circuit.

3.32

True random number generator (RNG)

All STM32F2xxx products embed a true RNG that delivers 32-bit random numbers

produced by an integrated analog circuit.

3.33

GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain,

with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)

or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog

alternate functions. All GPIOs are high-current-capable and have speed selection to better

manage internal noise, power consumption and electromagnetic emission.

The I/O alternate function configuration can be locked if needed by following a specific

sequence in order to avoid spurious writing to the I/Os registers.

To provide fast I/O handling, the GPIOs are on the fast AHB1 bus with a clock up to

120 MHz that leads to a maximum I/O toggling speed of 60 MHz.

3.34

ADCs (analog-to-digital converters)

Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16

external channels, performing conversions in the single-shot or scan mode. In scan mode,

automatic conversion is performed on a selected group of analog inputs.

Additional logic functions embedded in the ADC interface allow:

•

Simultaneous sample and hold

•

Interleaved sample and hold

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