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STM32F107RC bảng dữ liệu(PDF) 30 Page - STMicroelectronics

tên linh kiện STM32F107RC
Giải thích chi tiết về linh kiện  Connectivity line, ARM-based 32-bit MCU
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STM32F107RC bảng dữ liệu(HTML) 30 Page - STMicroelectronics

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Pinouts and pin description
STM32F105xx, STM32F107xx
30/104
Doc ID 15274 Rev 6
A7
55
89
PB3
I/O FT
JTDO
SPI3_SCK / I2S3_CK
PB3 / TRACESWO/
TIM2_CH2 / SPI1_SCK
A6
56
90
PB4
I/O FT
NJTRST
SPI3_MISO
PB4 / TIM3_CH1/
SPI1_MISO
C5 57
91
PB5
I/O
PB5
I2C1_SMBA / SPI3_MOSI /
ETH_MII_PPS_OUT / I2S3_SD
ETH_RMII_PPS_OUT
TIM3_CH2/SPI1_MOSI/
CAN2_RX
B5
58
92
PB6
I/O FT
PB6
I2C1_SCL(7)/TIM4_CH1(7)
USART1_TX/CAN2_TX
A5
59
93
PB7
I/O FT
PB7
I2C1_SDA(7)/TIM4_CH2(7)
USART1_RX
D5 60
94
BOOT0
I
BOOT0
B4
61
95
PB8
I/O FT
PB8
TIM4_CH3(7)/ ETH_MII_TXD3
I2C1_SCL/CAN1_RX
A4
62
96
PB9
I/O FT
PB9
TIM4_CH4(7)
I2C1_SDA / CAN1_TX
D4
-
97
PE0
I/O FT
PE0
TIM4_ETR
C4
-
98
PE1
I/O FT
PE1
E5
63
99
VSS_3
SVSS_3
F5
64 100
VDD_3
SVDD_3
1.
I = input, O = output, S = supply, HiZ = high impedance.
2.
FT = 5 V tolerant. All I/Os are VDD capable.
3.
Function availability depends on the chosen device.
4.
If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
5.
PC13, PC14 and PC15 are supplied through the power switch, and so their use in output mode is limited: they can be used
only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time.
6.
Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
7.
This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual,
available from the STMicroelectronics website: www.st.com.
8.
SPI2/I2S2 and I2C2 are not available when the Ethernet is being used.
9.
For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the
functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 and BGA100 packages, PD0
and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and
debug configuration section in the STM32F10xxx reference manual.
Table 5.
Pin definitions (continued)
Pins
Pin name
Main
function(3)
(after reset)
Alternate functions(4)
Default
Remap



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