PIC18F4680ISPQTP datasheet(477/482 Pages) MICROCHIP

477 / 482 page

Preliminary

DS39625C-page 475

PIC18F2585/2680/4585/4680

Timer0 and Timer1 External Clock .......................... 437

Transition for Entry to Idle Mode ................................ 38

Transition for Entry to SEC_RUN Mode .................... 35

Transition for Entry to Sleep Mode ............................ 37

Transition for Two-speed Start-up

(INTOSC to HSPLL) ........................................ 354

Transition for Wake from Idle to Run Mode ............... 38

Transition for Wake from Sleep (HSPLL) ................... 37

Transition from RC_RUN Mode to

PRI_RUN Mode ................................................. 36

Transition from SEC_RUN Mode to

PRI_RUN Mode (HSPLL) .................................. 35

Transition to RC_RUN Mode ..................................... 36

Timing Diagrams and Specifications ................................ 433

A/D Conversion Requirements ................................ 450

AC Characteristics

Internal RC Accuracy ....................................... 434

Capture/Compare/PWM Requirements ................... 438

CLKO and I/O Requirements ................................... 435

EUSART Synchronous Receive

Requirements .................................................. 448

EUSART Synchronous Transmission

Requirements .................................................. 448

Example SPI Mode Requirements

Master Mode, CKE = 0 .................................... 440

Master Mode, CKE = 1 .................................... 441

Slave Mode, CKE = 0 ...................................... 442

Slave Mode, CKE = 1 ...................................... 443

External Clock Requirements .................................. 433

High/Low-Voltage Detect Characteristics ................ 430

I2C Bus Data Requirements (Slave Mode) .............. 445

Master SSP I2C Bus Data Requirements ................ 447

Master SSP I2C Bus Start/Stop Bits

Requirements .................................................. 446

Parallel Slave Port Requirements

(PIC18F4585/4680) ......................................... 439

PLL Clock ................................................................. 434

Reset, Watchdog Timer, Oscillator Start-up

Timer, Power-up Timer and Brown-out

Reset Requirements ........................................ 436

Timer0 and Timer1 External Clock

Requirements .................................................. 437

Top-of-Stack Access .......................................................... 62

TRISE Register

PSPMODE Bit ......................................................... 138

TSTFSZ ........................................................................... 401

Two-Speed Start-up ................................................. 343, 354

Two-Word Instructions

Example Cases ......................................................... 66

TXSTA Register

BRGH Bit ................................................................. 231

Voltage Reference Specifications .................................... 429

Watchdog Timer (WDT) ........................................... 343, 352

Associated Registers ............................................... 353

Control Register ....................................................... 352

During Oscillator Failure .......................................... 355

Programming Considerations .................................. 352

WCOL ...................................................... 215, 216, 217, 220

WCOL Status Flag ................................... 215, 216, 217, 220

WWW Address ................................................................ 476

WWW, On-Line Support ...................................................... 5

XORLW ........................................................................... 401

XORWF ........................................................................... 402

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