PIC18F4680ISPQTP datasheet(266/482 Pages) MICROCHIP

266 / 482 page

PIC18F2585/2680/4585/4680

DS39625C-page 264

Preliminary

FIGURE 21-1:

COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

21.2

Voltage Reference Accuracy/Error

The full range of voltage reference cannot be realized

due to the construction of the module. The transistors

on the top and bottom of the resistor ladder network

(Figure 21-1) keep CVREF from approaching the

reference source rails. The voltage reference is derived

from the reference source; therefore, the CVREF output

changes with fluctuations in that source. The tested

absolute accuracy of the voltage reference can be

found in Section 27.0 “Electrical Characteristics”.

21.3

Operation During Sleep

When the device wakes up from Sleep through an

interrupt or a Watchdog Timer time-out, the contents of

the CVRCON register are not affected. To minimize

current consumption in Sleep mode, the voltage

reference should be disabled.

21.4

Effects of a Reset

A device Reset disables the voltage reference by

clearing bit CVREN (CVRCON<7>). This Reset also

disconnects the reference from the RA0 pin by clearing

bit CVROE (CVRCON<6>) and selects the high-voltage

range by clearing bit CVRR (CVRCON<5>). The CVR

value select bits are also cleared.

21.5

Connection Considerations

The voltage reference module operates independently

of the comparator module. The output of the reference

generator may be connected to the RA0 pin if the

TRISA<0> bit and the CVROE bit are both set.

Enabling the voltage reference output onto the RA0

pin, with an input signal present, will increase current

consumption. Connecting RA0 as a digital output with

CVRSS

enabled

will

also

increase

current

consumption.

The RA0 pin can be used as a simple D/A output with

limited drive capability. Due to the limited current drive

capability, a buffer must be used on the voltage

reference output for external connections to VREF.

Figure 21-2 shows an example buffering technique.

CVR3:CVR0

CVREN

CVRSS = 0

VDD

VREF+

CVRSS = 1

CVRSS = 0

VREF-

CVRSS = 1

16 Steps

CVRR

CVREF

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