PIC18F4680ISPQTP datasheet(242/482 Pages) MICROCHIP

242 / 482 page

PIC18F2585/2680/4585/4680

DS39625C-page 240

Preliminary

18.2.4

AUTO-WAKE-UP ON SYNC BREAK

CHARACTER

During Sleep mode, all clocks to the EUSART are

suspended. Because of this, the Baud Rate Generator

is inactive and a proper byte reception cannot be

performed. The auto-wake-up feature allows the

controller to wake-up due to activity on the RX/DT line

while the EUSART is operating in Asynchronous mode.

The auto-wake-up feature is enabled by setting the

WUE bit (BAUDCON<1>). Once set, the typical receive

sequence on RX/DT is disabled and the EUSART

remains in an Idle state, monitoring for a wake-up event

independent of the CPU mode. A wake-up event

consists of a high-to-low transition on the RX/DT line.

(This coincides with the start of a Sync Break or a

Wake-up Signal character for the LIN protocol.)

Following a wake-up event, the module generates an

RCIF interrupt. The interrupt is generated synchro-

nously to the Q clocks in normal operating modes

(Figure 18-8) and asynchronously, if the device is in

Sleep mode (Figure 18-9). The interrupt condition is

cleared by reading the RCREG register.

The WUE bit is automatically cleared once a low-to-high

transition is observed on the RX line following the

wake-up event. At this point, the EUSART module is in

Idle mode and returns to normal operation. This signals

to the user that the Sync Break event is over.

18.2.4.1

Special Considerations Using

Auto-Wake-up

Since auto-wake-up functions by sensing rising edge

transitions on RX/DT, information with any state

changes before the Stop bit may signal a false

end-of-character and cause data or framing errors. To

work properly, therefore, the initial character in the trans-

mission must be all ‘0’s. This can be 00h (8 bytes) for

standard RS-232 devices or 000h (12 bits) for LIN bus.

Oscillator start-up time must also be considered,

especially in applications using oscillators with longer

start-up intervals (i.e., XT or HS mode). The Sync

Break (or Wake-up Signal) character must be of

sufficient length and be followed by a sufficient interval

to allow enough time for the selected oscillator to start

and provide proper initialization of the EUSART.

18.2.4.2

Special Considerations Using

the WUE Bit

The timing of WUE and RCIF events may cause some

confusion when it comes to determining the validity of

received data. As noted, setting the WUE bit places the

EUSART in an Idle mode. The wake-up event causes

a receive interrupt by setting the RCIF bit. The WUE bit

is cleared after this when a rising edge is seen on

RX/DT. The interrupt condition is then cleared by

reading the RCREG register. Ordinarily, the data in

RCREG will be dummy data and should be discarded.

The fact that the WUE bit has been cleared (or is still

set) and the RCIF flag is set should not be used as an

indicator of the integrity of the data in RCREG. Users

should consider implementing a parallel method in

firmware to verify received data integrity.

To assure that no actual data is lost, check the RCIDL

bit to verify that a receive operation is not in process. If

a receive operation is not occurring, the WUE bit may

then be set just prior to entering the Sleep mode.

FIGURE 18-8:

AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION

FIGURE 18-9:

AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

WUE bit(1)

RX/DT Line

RCIF

Note 1:

The EUSART remains in Idle while the WUE bit is set.

Bit set by user

Auto-Cleared

Cleared due to user read of RCREG

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

WUE bit(2)

RX/DT Line

RCIF

SLEEP

Command Executed

Note 1:

If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur while the

stposc signal is still active.

This sequence should not depend on the presence of Q clocks.

The EUSART remains in Idle while the WUE bit is set.

Sleep Ends

Auto-Cleared

Note 1

Cleared due to user read of RCREG

Bit set by user

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