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PIC18F4680ISPQTP bảng dữ liệu(PDF) 241 Page - Microchip Technology

tên linh kiện PIC18F4680ISPQTP
Giải thích chi tiết về linh kiện  28/40/44-Pin Enhanced Flash Microcontrollers with ECAN??Technology, 10-Bit A/D and nanoWatt Technology
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nhà sản xuất  MICROCHIP [Microchip Technology]
Trang chủ  http://www.microchip.com
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PIC18F4680ISPQTP bảng dữ liệu(HTML) 241 Page - Microchip Technology

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© 2007 Microchip Technology Inc.
Preliminary
DS39625C-page 239
PIC18F2585/2680/4585/4680
FIGURE 18-7:
ASYNCHRONOUS RECEPTION
TABLE 18-6:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Start
bit
bit 7/8
bit 1
bit 0
bit 7/8
bit 0
Stop
bit
Start
bit
Start
bit
bit 7/8
Stop
bit
RX (pin)
Rcv Buffer Reg
Rcv Shift Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG
Word 2
RCREG
Stop
bit
Note:
This timing diagram shows three words appearing on the RX input.
The RCREG (receive buffer) is read after the third word
causing the OERR (overrun) bit to be set.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON
GIE/GIEH PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
49
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
52
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
52
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
52
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
51
RCREG
EUSART Receive Register
51
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
51
BAUDCON
ABDOVF
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN
51
SPBRGH
EUSART Baud Rate Generator Register High Byte
51
SPBRG
EUSART Baud Rate Generator Register Low Byte
51
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1:
Reserved in PIC18F2X8X devices; always maintain these bits clear.



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