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STM8S005C6T6 bảng dữ liệu(PDF) 45 Page - STMicroelectronics |
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STM8S005C6T6 bảng dữ liệu(HTML) 45 Page - STMicroelectronics |
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45 / 103 page ![]() Factory default setting Option bits Option byte no. Option name Addr. 0 1 2 3 4 5 6 7 FFh Reserved NOPT6 0x480C 00h Reserved OPT7 Reserved 0x480D FFh Reserved NOPT7 0x480E 00h BL[7:0] OPTBL Bootloader 0x487E FFh NBL[7:0] NOPTBL 0x487F Table 12: Option byte description Description Option byte no. ROP[7:0] Memory readout protection (ROP) OPT0 AAh: Enable readout protection (write access via SWIM protocol) Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM memory readout protection for details. UBC[7:0] User boot code area OPT1 0x00: no UBC, no write-protection 0x01: Page 0 to 1 defined as UBC, memory write-protected 0x02: Page 0 to 3 defined as UBC, memory write-protected 0x03: Page 0 to 4 defined as UBC, memory write-protected ... 0x3E: Pages 0 to 63 defined as UBC, memory write-protected Other values: Reserved Note: Refer to the family reference manual (RM0016) section on Flash write protection for more details. AFR[7:0] OPT2 Refer to following table for the alternate function remapping decriptions of bits [7:2]. HSITRIM:High speed internal clock trimming register size OPT3 0: 3-bit trimming supported in CLK_HSITRIMR register 1: 4-bit trimming supported in CLK_HSITRIMR register 45/103 DocID022186 Rev 3 Option bytes STM8S005K6 STM8S005C6 |
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