28F256 datasheet(6/35 Pages) AMD

6 / 35 page

Am28F256

PIN DESCRIPTION

A0–A14

Address Inputs for memory locations. Internal latches

hold addresses during write cycles.

CE# (E#)

Chip Enable active low input activates the chip’s control

logic and input buffers. Chip Enable high will deselect

the device and operates the chip in stand-by mode.

DQ0–DQ7

Data Inputs during memor y write cycles. Internal

latches hold data during write cycles. Data Outputs

during memory read cycles.

No Connect-corresponding pin is not connected

internally to the die.

OE# (G#)

Output Enable active low input gates the outputs of the

device through the data buffers dur ing memor y

read cycles. Output Enable is high during command

sequencing and program/erase operations.

Power supply for device operation. (5.0 V

± 5% or 10%)

Program voltage input. VPP must be at high voltage in

order to write to the command register. The command

memory array contents. Memory contents cannot be

altered when VPP ≤ VCC +2 V.

Ground

WE# (W#)

Write Enable active low input controls the write function

of the command register to the memory array. The

target address is latched on the falling edge of the

Write Enable pulse and the appropriate data is latched

on the rising edge of the pulse. Write Enable high

inhibits writing to the device.

28F256 bảng dữ liệu(PDF) 6 Page - Advanced Micro Devices