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AM85C30 bảng dữ liệu(PDF) 171 Page - Advanced Micro Devices |
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AM85C30 bảng dữ liệu(HTML) 171 Page - Advanced Micro Devices |
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171 / 194 page  SCC Application Notes AMD 7–22 QC QB A23 CS Am8530H CLK CLR B A QD Am29809 A18 A11 A 1 A 4 LDS R/ W INT RD D/ C 74LS74 CP D Q CLK 74LS32 74LS32 74LS04 74LS02 ANYE ACK Am29806 CLK DTACK 68000 74LS04 CLK EI 0 1 2 3 4 A0 A1 A2 A 1 A 2 A 3 A B C 1 2 3 4 INTA A B C G2A A B CLR CLK 7 74LS138 Q E QF OC 74LS16 CLK INTA WR 74LS138 PCLK CLK/2 12 3 74LS04 G A 7 A 0 CLK EOUT CLK/2 VCC G EOUT • • • A0 • • • S1 S0 PRE 8 6 A5 • • • A10 A 3 IPL 0 IPL 1 IPL 2 FC 1 FC 2 FC 0 AS OTHER INTRRUPTS INTA FOR OTHER INTERRUPTING DEVICES 74LS164 BIP SWITCHES OR SOLDER BRIDGES FOR SETTING ADDRESS 74LS04 CONNECT FOR DESIRED NUMBER OF WAIT STATES 74LS164 74LS02 74LS04 74LS04 74LS148 A5 OSC Figure 7–12. Am8530H to 68000 Connection with Interrupts Using SSI and MSI The data bus between the 68000 and the Am8530H are directly linked together. The Am29806 decodes the address and generates CS for the peripheral and produces ANYE, which is used by the 74LS164, to generate Wait States. The 74LS164 controls the num- ber of wait states by the “C” input which in turn controls the DTACK signal to the CPU. This allows RD and WR to obtain the required 400 ns width. A1 generates the C/D input to the Am8530H while the remaining address lines are connected to the Am29809 ad- dress comparator. The Am29809 Comparator and the Am29806 Comparator/Decoder provides high-speed address selection as well as an open collector acknowledge driver. This allows memories and peripherals to be conveniently wire-ORed to the processor’s DTACK pin. This inter- face does not provide a hardware reset; therefore, it is necessary to do a dummy read to the control port before issuing a software reset. |
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