AM85C30 datasheet(78/194 Pages) AMD

78 / 194 page

Data Communication Modes Functional Description

AMD

4–26

10216A-018A

C10 C11 C12 C13 C14 C15

Residue

Code

0 1 2

0 1 1

C 4

C 8

C10 C11 C12 C13 C14

C 9

C10 C11 C12 C13 C14 C15

Residue

Code

0 1 2

1 1 1

C 7 C8

C10 C11 C12 C13

C10 C11 C12 C13 C14 C15

Residue

Code

0 1 2

0 0 0

C 2

C10 C11 C12

C10 C11 C12 C13 C14 C15

Residue

Code

0 1 2

1 0 0

C10 C11

Residue

Code

0 1 2

0 1 0

C 0

C 6

C10

Residue

Code

0 1 2

1 1 0

Residue

Code

0 1 2

0 0 1

(No Residue)

(One Residue Bit)

(Two Residue Bits)

(3 Residue Bits)

(4 Residue Bits)

(5 Residue Bits)

(6 Residue Bits)

Residue

Code

0 1 2

1 0 1

(7 Residue Bits)

Figure 4–18. Eight Bits/Character

4.7.3

End of Frame (EOF)

Once character assembly begins characters are assembled according to the number of

bits per character specified until an end of frame flag is detected. When this condition is

detected, the receiver transfers the contents of the Receive Shift Register into the Re-

ceive Data FIFO regardless of the number of bits assembled, and the Residue Code, the

CRC Error bit, and EOF Status bit are latched in the Receive Error FIFO.

If either the Rx Interrupt on Special Condition Only or Rx Interrupt on First Character or

Special Condition mode is selected, an interrupt will be generated when the EOF Status

bit reaches the top of the Error FIFO, but only after its associated character is read from

the Receive Data FIFO. When the character is read the FIFO will be locked, that is, the

EOF Status bit remains set for all subsequent characters received until reset by the Error

Reset Command. The processor may then read RR1 to determine the CRC status and

Residue Code of the frame and issue an Error Reset command in WR0 to unlock the Re-

ceive Data FIFO.

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