AM85C30 datasheet(108/194 Pages) AMD

108 / 194 page

Support Circuitry Programming

AMD

5–14

With all three of these data encoding methods there will be at least one transition in every

bit cell, and in FM mode the DPLL is designed to expect this transition. In particular, if no

transition occurs between the middle of count 12 and the middle of count 19, the DPLL is

probably not locked onto the data properly. When the DPLL misses an edge the One

Clock Missing bit in RR10 is set to ‘1’ and latched. It will hold this value until a Reset

Missing Clock command is issued in WR14 or until the DPLL is disabled or programmed

to enter the Search mode.

Upon missing this one edge the DPLL takes no other action and does not modify its count

during the next counting cycle. However, if the DPLL does not see an edge between the

middle of count 12 and the middle of count 19 in two successive 0 to 31 count cycles, a

line Figure 5–7. DPLL Operating Example error condition is assumed. If this occurs, the

two Clocks Missing bits in RR10 are set to ‘1’ and latched. At the same time the DPLL

enters the Search mode. The DPLL makes the decision to enter Search mode during

count 2, where both the receive and transmit clock outputs are Low. This prevents any

glitches on the clock outputs when Search mode is entered. While in Search mode no

clock outputs are provided by the DPLL. The two Clocks Missing bit in RR10 is latched

until a Reset Missing Clock command is issued in WR14, or until the DPLL is disabled or

programmed to enter the Search mode.

In NRZI Mode of operation and while the DPLL is disabled, the One and Two Clock Miss-

ing bits in RR10 will be reset to ‘0’.

Bit Cell

Count 16

811

Correction

Ignored

No Change

RX DPLL Out

–1

TX DPLL Out

Figure 5–8. DPLL in FM Mode

Data

Manchester

RX DPLL Out

TX DPLL Out

Figure 5–9. Manchester Clock Recovery

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