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AM79C988BJC bảng dữ liệu(PDF) 18 Page - Advanced Micro Devices |
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AM79C988BJC bảng dữ liệu(HTML) 18 Page - Advanced Micro Devices |
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18 / 25 page  18 Am79C988A PRELIMINARY SWITCHING CHARACTERISTICS over operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Max Unit Clock and Reset Timing tCLK CLK Clock Period (Note 1) 49.995 50.005 ns tCLKH CLK Clock High 20 30 ns tCLKL CLK Clock Low 20 30 ns tCLKR CLK Rise Time (Note 1) - 10 ns tCLKF CLK Fall Time (Note 1) - 10 ns tRST Reset Pulse Width (RST pin LOW) 4 - µs tPRST Reset Pulse Width at Power Up 150 - µs Transmit Timing tPWODO PDO Pulse Width Accept/ Reject Thresh- old Input > VASQ (Max) (Note 3) 15 35 ns tPWKDO PDO Pulse Width Maintain/Turn-Off Threshold Input > VASQ (Max) (Note 4) 110 200 ns tTON Transmit Start-Up Delay - 300 ns tTSD Transmit Static Propagation Delay (PDO to TXD) - 200 ns tTETD Transmit End of Transmission (for TXD) 250 450 ns tPERLP Idle Signal Period (Note 7) 8 24 ms tPWLP Link Pulse Width (Note 1) 75 120 ns tJA Transmit Jabber Activation Time (Note 7) 20 150 ms tJR Transmit Jabber Reset Time (Note 7) 250 750 ms tJREC Transmit Jabber Recovery Time (Mini- mum time gap between packets to prevent Jabber activation) (Note 1) 1.0 - µs tDODION PDO to PDI Start-up Delay 300 ns tDODISD PDO to PDI Static Propagation Delay - 100 ns Receive Timing tPWORD RXD Pulse Width Accept/Reject Threshold (Note 5) 5 35 ns tPWKRD RXD Pulse Width Maintain/Turn-Off Threshold (Note 6) 136 200 ns tRON Receiver Start-up Delay (RXD to PDI) 200 400 ns tRVD First Validly Timed Bits - tRON +100 ns tRSD Receiver Static Propagation Delay (RXD to PDI) - 70 ns tRETD PDI End of Transmission 200 - ns tRR PDI, PCI Rise Time (Note 1) - 10 ns tRF PDI, PCI Fall Time (Note 1) - 10 ns tRM PDI, PCI Rise and Fall Time Mismatch (tRR - tRF) (Note 1) - 5 ns Collision Timing tCON Collision Turn On Delay - 500 ns tCOFF Collision Turn Off Delay - 500 ns tCPER Collision Period (Note 1) 87 117 ns tCPW Collision Output Pulse Width (Note 1) 40 60 ns Serial Interface Timing tSDSU CLK to DIR Setup Time (Note 7) 10 - ns tSDHD DIR Hold Time (Note 7) 10 - ns tSSSU CLK to SDATA Setup Time (Note 7) 10 - ns tSSHD CLK to SDATA Hold Time (Note 7) 10 - ns tSSDO CLK to Output Delay - 40 ns |
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