AM79C978VCSLASHW datasheet(58/261 Pages) AMD

58 / 261 page

Am79C978

Note that the Am79C978 controller will always perform

a DWord transfer as long as it owns the buffer space,

even when there are less than four bytes to write. For

example, if there is only one byte left for the current re-

ceive frame, the Am79C978 controller will write a full

DWord, containing the last byte of the receive frame in

the least significant byte position (BSWP is cleared to

0, CSR3, bit 2). The content of the other three bytes is

undefined. The message byte count in the receive de-

scriptor always reflects the exact length of the received

frame.

Figure 31.

FIFO Burst Write at Start of Unaligned

Buffer

TheAm79C978 controller will continue transferring

FIFO data until the transmit FIFO is filled to its high

threshold (read transfers) or the receive FIFO is emp-

tied to its low threshold (write transfers), or the

Am79C978 controller is preempted and the PCI La-

tency Timer is expired. The host should use the values

in the PCI MIN_GNT and MAX_LAT registers to deter-

mine the value for the PCI Latency Timer.

Figure 32.

FIFO Burst Write at End of Unaligned

Buffer

The exact number of total transfer cycles in the bus

mastership period is dependent on all of the following

variables: the settings of the FIFO watermarks, the

conditions of the FIFOs, the latency of the system bus

to the Am79C978 controller’s bus request, and the

speed of bus operation. The TRDY response time of

the memory device will also affect the number of trans-

fers, since the speed of the accesses will affect the

state of the FIFO. During accesses, the FIFO may be

filling or emptying on the network end. For example, on

a receive operation, a slower TRDY response will allow

additional data to accumulate inside of the FIFO. If the

accesses are slow enough, a complete DWord may be-

come available before the end of the bus mastership

period and, thereby, increase the number of transfers

in that period. The general rule is that the longer the

Bus Grant latency, the slower the bus transfer opera-

tions; the slower the clock speed, the higher the trans-

mit watermark; or the lower the receive watermark, the

longer the total burst length will be.

When a FIFO DMA burst operation is preempted, the

Am79C978 controller will not relinquish bus ownership

until the PCI Latency Timer expires.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

23456

0000

0111

PAR

DEVSEL

is sampled

0001

PAR

DATA

ADD

22206B-34

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

234567

0000

0111

PAR

DEVSEL

is sampled

1110

PAR

DATA

ADD

22206B-35

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