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AM79C976 bảng dữ liệu(PDF) 173 Page - Advanced Micro Devices |
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AM79C976 bảng dữ liệu(HTML) 173 Page - Advanced Micro Devices |
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173 / 309 page  8/01/00 Am79C976 173 P R E L I M INARY Control and Status Registers The Control and Status Registers (CSRs) are included for compatibility with older PCnet Family software. All CSR functions can be accessed more efficiently through the memory-mapped registers. The CSR space is accessible by performing accesses to the RDP (Register Data Port). The particular CSR that is read or written during an RDP access will de- pend upon the current setting of the RAP. RAP serves as a pointer into the CSR space. Am79C976 CSRs can be accessed at any time. For older PCnet family devices certain CSRs could only be accessed when the device is stopped. &65 $P & &RQWUROOHU 6WDWXV DQG&RQWURO 5HJLVWHU Certain bits in CSR0 indicate the cause of an interrupt. The register is designed so that these indicator bits are cleared by writing ones to those bit locations. This means that the software can read CSR0 and write back the value just read to clear the interrupt condition. Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15 ERR Obsolete function. Read/Write accessible. Read returns zero. 14 BABL Obsolete function. Read/Write accessible. Read returns zero. 13 CERR Obsolete function. Read/Write accessible. Read returns zero. 12 MISS Obsolete function. Read/Write accessible. Read returns zero. 11 MERR Obsolete function. Read/Write accessible. Read returns zero. 10 RINT Receive Interrupt is set by the Am79C976 controller after the last descriptor of a receive frame has been updated by writing a 0 to the OWNership bit. RINT may also be set when the first descrip- tor of a receive frame has been updated by writing a 0 to the OWNership bit if the LAPPEN bit of CSR3 has been set to a 1. When RINT is set, INTA is assert- ed if IENA is 1 and the mask bit RINTM (CSR3, bit 10) is 0. Read/Write accessible. RINT is cleared by the host by writing a 1. Writing a 0 has no effect. RINT is cleared by H_RESET, S_RESET, or by setting the STOP bit. 9 TINT Transmit Interrupt is set by the Am79C976 controller after the OWN bit in the last descriptor of a transmit frame has been cleared to indicate the frame has been copied to the transmit FIFO. When TINT is set, INTA is assert- ed if IENA is 1 and the mask bit TINTM (CSR3, bit 9) is 0. Read/Write accessible. TINT is cleared by the host by writing a 1. Writing a 0 has no effect. TINT is cleared by H_RESET, S_RESET, or by setting the STOP bit. 8 IDON Initialization Done is set by the Am79C976 controller after the initialization sequence has com- pleted. When IDON is set, the Am79C976 controller has read the initialization block from mem- ory. When IDON is set, INTA is as- serted if IENA is 1 and the mask bit IDONM (CSR3, bit 8) is 0. Read/Write accessible. IDON is cleared by the host by writing a 1. Writing a 0 has no effect. IDON is cleared by H_RESET, S_RESET, or by setting the STOP bit. 7 INTR Interrupt Flag indicates that one or more following interrupt caus- ing conditions has occurred: IDON, RINT, SINT, TINT, TX- STRT, UINT, STINT, MREINT, MCCINT, MCCIINT, MIIPDTINT, MAPINT, MPINT, APINT, LCINT, SPNDINT and the associated mask or enable bit is pro- grammed to allow the event to cause an interrupt. If IENA is set to 1 and INTR is set, INTA will be active. When INTR is set by SINT or SLPINT, INTA will be active in- dependent of the state of IENA. |
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