AM79C976 datasheet(268/309 Pages) AMD

268 / 309 page

268

Am79C976

8/01/00

P R E L I M INARY

Notes:

1. IOL1 applies to all non LED pins.

IOL2 applies to LED0, LED1, LED2, LED3, and WUMI.

IOL3 applies to AD[31:0], C/BE[3:0], PAR, and REQ pins in a 5 V signaling environment.

IOL4 applies to FRAME, TRDY, IRDY, DEVSEL, STOP, SERR, PERR, and INTA.

2. VOH does not apply to open-drain output pins.

3. IOZ applies to all 3-state output and bidirectional pins, except the PME pin.

4. IIX applies to all input pins except PME, TDI, TCK, and TMS pins. Tests are performed at VIN = 0 V and at VDD only.

5. IIL and IIH apply to the TDI, TCK, and TMS pins.

6. IIX_PME applies to the PME pin only. Tests are performed at VIN = 0 V and 5.5 V only.

7. Parameter not tested. Value determined by characterization.

8. CCLK applies only to the CLK pin.

9. CIDSEL applies only to the IDSEL pin.

Power Supply Current

IDD

Dynamic Current

PCI CLK at 33 MHz, MII Interface at 25 MHz, Full-

Duplex operation, SRAM at 90 MHz

340

IDD_WU1

Wake-up current when the device is

in the D1, D2, or D3 state and the

PCI bus is in the B0 or B1 state.

PCI CLK at 33 MHz, MII Interface at 25 MHz,

SRAM at 90 MHz. Device at Magic Packet or

OnNow mode, receiving non-matching packets

280

IDD_WU2

Wake-up current when the device is

in the D2 or D3 state and the PCI bus

is in the B2 or B3 state.

PCI CLK LOW, MII Interface at 25 MHz, SRAM at

90 MHz, PG LOW, Device at Magic Packet or

OnNow mode, receiving non-matching packets

265

IDD_S

Static IDD

PCI CLK, SRAM pins and MII pins LOW.

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