AM79C976 datasheet(212/309 Pages) AMD

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212

Am79C976

8/01/00

P R E L I M INARY

ESK

EEPROM Serial Clock. This bit

and the EDI/EDO bit are used to

control

host

access

the

EEPROM. Values programmed

to this bit are placed onto the

EESK pin at the rising edge of the

next clock following bit program-

ming, except when the PREAD

bit is set to 1 or the EEN bit is set

to 0. If both the ESK bit and the

EDI/EDO bit values are changed

during one BCR19 write opera-

tion, while EEN = 1, then setup

and hold times of the EEDI pin

value with respect to the EESK

signal edge are not guaranteed.

ESK has no effect on the EESK

pin unless the PREAD bit is set to

0 and the EEN bit is set to 1.

Read/Write accessible. ESK is

reset to 0 by H_RESET and is not

affected by S_RESET or STOP.

EDI/EDO

EEPROM

Data

In/EEPROM

Data Out. Data that is written to

this bit will appear on the EEDI

output of the interface, except

when the PREAD bit is set to 1 or

the EEN bit is set to 0. Data that

is read from this bit reflects the

value of the EEDO input of the in-

terface.

EDI/EDO has no effect on the

EEDI pin unless the PREAD bit is

set to 0 and the EEN bit is set to

Read/Write accessible. EDI/EDO

is reset to 0 by H_RESET and is

not affected by S_RESET or

STOP.

%&56RIWZDUH 6W\OH

This register is an alias of the location CSR58. Accesses

to and from this register are equivalent to accesses to

CSR58.

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-11

RES

Reserved locations. Written as

zeros and read as undefined.

APERREN

Obsolete function. Writing has no

effect. Read as undefined.

RES

Reserved locations. Written as

zeros; read as undefined.

SSIZE32

Software Size 32 bits. When set,

this

bit

indicates

that

the

Am79C976

controller

utilizes

32-bit software structures for the

initialization block and the trans-

mit and receive descriptor en-

tries.

When

cleared,

this bit

indicates that the Am79C976

controller utilizes 16-bit software

structures for the initialization

block and the transmit and re-

ceive descriptor entries. In this

mode, the Am79C976 controller

is backwards compatible with the

Am7990 LANCE and Am79C960

PCnet-ISA controllers.

The value of SSIZE32 is deter-

mined by the Am79C976 control-

ler according to the setting of the

Software Style (SWSTYLE, bits

7-0 of this register).

SSIZE32 is read only; write oper-

ations will be ignored. SSIZE32

will be cleared after H_RESET

(since SWSTYLE defaults to 0)

and is not affected by S_RESET

or STOP.

If SSIZE32 is reset, then bits

IADR[31:24] of CSR2 will be

used to generate values for the

upper 8 bits of the 32-bit address

bus during master accesses initi-

ated by the Am79C976 controller.

This action is required, since the

16-bit software structures speci-

fied by the SSIZE32 = 0 setting

will yield only 24 bits of address

for Am79C976

controller bus

master accesses.

If SSIZE32 is set, then the soft-

ware structures that are common

to the Am79C976 controller and

the host system will supply a full

32 bits for each address pointer

that is needed by the Am79C976

controller for performing master

accesses.

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