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AM79C976 bảng dữ liệu(PDF) 194 Page - Advanced Micro Devices |
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AM79C976 bảng dữ liệu(HTML) 194 Page - Advanced Micro Devices |
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194 / 309 page  194 Am79C976 8/01/00 P R E L I M INARY 31-0 RES Reserved locations. Written as zeros and read as undefined. &65 2Q1RZ 3RZHU 0RGH5HJLVWHU Note: Bits 10-0 in this register are programmable through the EEPROM. Bit Name Description 31-11 RES Reserved locations. Written as zeros and read as undefined. 10 PME_EN_OVR PME_EN Overwrite. When this bit is set and the MPMAT or LC- DET bit is set, the PME pin will al- ways be asserted regardless of the state of PME_EN bit. Read/Write accessible. Cleared by H_RESET and is not affected by S_RESET or setting the STOP bit. 9 LCDET Link Change Detected. This bit is set when the MII auto-polling log- ic detects a change in link status and the LCMODE bit is set. This bit can be cleared to 0 either by writing 1 to CSR116, bit 9 or by writing 1 to STAT0, bit 10. LCDET is cleared when power is initially applied (POR). Read/Write accessible. 8 LCMODE Link Change Wake-up Mode. When this bit is set to 1, the LC- DET bit gets set when the MII auto polling logic detects a Link Change. Read/Write accessible. Cleared by H_RESET and is not affected by S_RESET or setting the STOP bit. 7 PMAT Pattern Matched. This bit is set when the PMMODE bit is set and an OnNow pattern match occurs. This bit can be cleared to 0 either by writing 0 to CSR116, bit 7 or by writing 1 to STAT0, bit 12. PMAT is cleared when power is initially applied (POR). Read/Write accessible. 6 EMPPLBA Magic Packet Physical Logical Broadcast Accept. If both EMP- PLBA and MPPLBA (CSR5, bit 5) are at their default value of 0, the Am79C976 controller will only de- tect a Magic Packet frame if the destination address of the packet matches the content of the physi- cal address register (PADR). If ei- ther EMPPLBA or MPPLBA is set to 1, the destination address of the Magic Packet frame can be unicast, multicast, or broadcast. Note that the setting of EMPPL- BA and MPPLBA only affects the address detection of the Magic Packet frame. The Magic Packet frame’s data sequence must be made up of 16 consecutive phys- ical addresses (PADR[47:0]) re- gardless of what kind of destination address it has. Read/Write accessible. EMPPLBA is set to 0 by H_RESET or S_RESET and is not affected by setting the STOP bit. 5 MPMAT Magic Packet Match. This bit is set when PCnet-FAST+ detects a Magic Packet while it is in the Magic Packet mode. This bit can be cleared to 0 either by writing 0 to CSR116, bit 5 or by writing 1 to STAT0, bit 11. MPMAT is cleared when power is initially applied (POR). Read/Write accessible. 4 MPPEN Magic Packet Pin Enable. When this bit is set, the device enters the Magic Packet mode when the PG input goes LOW or MPEN bit (CSR5, bit 2) gets set to 1. This bit is OR’ed with MPEN (CSR5, bit 2). Read/Write accessible. Cleared by H_RESET and is not affected |
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