AM79C972BVCW datasheet(75/130 Pages) AMD

75 / 130 page

Am79C972

adding the input to clock setup time for Flash/EPRO in-

puts (ts_D) from the time defined by ROMTMG:

tACC = ROMTMG * CLK period * CLK_FAC - (tv_A_D) -

(ts_D)

The timing diagram in Figure 42 assumes the default

programming of ROMTMG (1001b = 9 CLK). After

reading the first byte, the Am79C972 controller reads in

three more bytes by incrementing the lower portion of

the ROM address. After the last byte is strobed in,

TRDY will be asserted on clock 50. When the host tries

to perform a burst read of the Expansion ROM, the

Am79C972 controller will disconnect the access at the

second data phase.

The host must program the Expansion ROM Base Ad-

dress register in the PCI configuration space before the

first access to the Expansion ROM. The Am79C972

controller will not react to any access to the Expansion

ROM until both MEMEN (PCI Command register, bit 1)

and ROMEN (PCI Expansion ROM Base Address reg-

ister, bit 0) are set to 1. After the Expansion ROM is

enabled, the Am79C972 controller will claim all memory

read accesses with an address between ROMBASE

and ROMBASE + 1M - 4 (ROMBASE, PCI Expansion

ROM Base Address register, bits 31-20). The address

output to the Expansion ROM is the offset from the ad-

dress on the PCI bus to ROMBASE. The Am79C972

controller aliases all accesses to the Expansion ROM

of the command types Memory Read Multiple and Mem-

ory Read Line to the basic Memory Read command.

Figure 40.

EPROM Only Configuration for the Expansion Bus (64K EPROM)

EBUA_EBA[7:0]

EBDA[15:8]

EBD[7:0]

EBWE

EROMCS

A[15:8]

A[7:0]

DQ[7:0]

Am79C972

EPROM

AS_EBOE

21485C-43

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