công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

AM79C960KCW bảng dữ liệu(PDF) 98 Page - Advanced Micro Devices

tên linh kiện AM79C960KCW
Giải thích chi tiết về linh kiện  PCnetTM-ISA Single-Chip Ethernet Controller
PDF  127 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  AMD [Advanced Micro Devices]
Trang chủ  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM79C960KCW bảng dữ liệu(HTML) 98 Page - Advanced Micro Devices

Back Button AM79C960KCW Datasheet HTML 94Page - Advanced Micro Devices AM79C960KCW Datasheet HTML 95Page - Advanced Micro Devices AM79C960KCW Datasheet HTML 96Page - Advanced Micro Devices AM79C960KCW Datasheet HTML 97Page - Advanced Micro Devices AM79C960KCW Datasheet HTML 98Page - Advanced Micro Devices AM79C960KCW Datasheet HTML 99Page - Advanced Micro Devices AM79C960KCW Datasheet HTML 100Page - Advanced Micro Devices AM79C960KCW Datasheet HTML 101Page - Advanced Micro Devices AM79C960KCW Datasheet HTML 102Page - Advanced Micro Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 98 / 127 page
background image
P R E L I M I N A R Y
AMD
1-440
Am79C960
SWITCHING CHARACTERISTICS: GPSI
Notes:
1. CLSN must be asserted for a continuous period of 110 ns or more. Assertion for less than 110 ns period may or may
not result in CLSN recognition.
2. RCLK should meet jitter requirements of IEEE 802.3 specification.
3. CLSN assertion before 51.2
µs will be indicated as a normal collision. CLSN assertion after 51.2 µs will be
considered as a Late Receive Collision.
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
Transmit Timing
tGPT1
TCLK Period (802.3 Compliant)
99.99
100.01
ns
tGPT2
TCLK HIGH Time
40
60
ns
tGPT3
TX and TENA Delay from
↑ TCLK
0
70
ns
tGPT4
RENA Setup Before
↑ TCLK (Last Bit)
210
ns
tGPT5
RENA Hold After
↓ TENA
0
ns
tGPT6
CLSN Active Time to Trigger Collision
(Note 1)
110
ns
tGPT7
CLSN Active to
↓ RENA to Prevent
LCAR Assertion
0
ns
tGPT8
CLSN Active to
↓ RENA for SQE
Hearbeat Window
0
4.0
µs
Tgpt9
CLSN Active to
↑ Rena for Normal Collision
0
51.2
µs
Receive Timing
tGPR1
RCLK Period
(Note 2)
80
120
ns
tGPR2
RCLK HIGH Time
(Note 2)
30
80
ns
tGPR3
RCLK LOW Time
(Note 2)
30
80
ns
tGPR4
RX and RENA Setup to
↑ RCLK
15
ns
tGPR5
RX Hold After
↑ RCLK
15
ns
tGPR6
RENA Hold After
↓ RCLK
0
ns
tGPR7
CLSN Active to First
↑ RCLK
(Collision Recognition)
0
ns
tGPR8
CLSN Active to
↑ RCLK for
Address Type Designation Bit
(Note 3)
51.2
µs
tGPR9
CLSN Setup to Last
↑ RCLK for
Collision Recognition
210
ns
tGPR10
CLSN Active
110
ns
tGPR11
CLSN Inactive Setup to First
↑ RCLK
300
ns
tGPR12
CLSN Inactive Hold to Last
↑ RCLK
300
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com