AM79C30AVC datasheet(1/101 Pages) AMD

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FINAL

This document contains information on a product under development at Advanced Micro Devices. The information

is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed

product without notice.

Publication# 09893 Rev: H Amendment/0

Issue Date: December 1998

Am79C30A/32A

Digital Subscriber Controller™ (DSC™) Circuit

DISTINCTIVE CHARACTERISTICS

s Combines CCITT I.430 S/T-Interface Transceiver,

D-Channel LAPD Processor, Audio

s Processor (DSC device only), and IOM-2

Interface in a single chip

s Special operating modes allow realization of

CCITT I.430 power-compliant terminal

equipment

s S- or T-Interface Transceiver

— Level 1 Physical Layer Controller

— Supports point-to-point, short and extended

passive bus configurations

— Provides multiframe support

s Certified protocol software support available

s CMOS technology, TTL compatible

s D-channel processing capability

— Flag generation/detection

— CRC generation/checking

— Zero insertion/deletion

— Four 2-byte address detectors

— 32-byte receive and 16-byte transmit FIFOs

BLOCK DIAGRAM

CAP1

AINA

AREF

AINB

EAR1

EAR2

LS1

LS2

Main Audio

Processor (MAP)

SBIN

SCLK

BCL/CH2STRB*

SBIOUT

SFS

HSW

CAP2

(Am79C30A

Only)

XTAL1

XTAL2

MCLK

CS

WR

RD

Peripheral Port

(PP)

B-channel Multiplexer

(MUX)

Microprocessor Interface

(MUX)

Oscillator

(OSC)

Ba

Bb

Bc

Bd

Be

Bf

B1

B2

S/T Line

Interface Unit

(LIU)

D

Channel

LOUT1

LOUT2

LIN1

LIN2

D-Channel Data

Link Controller

(DLC)

D

Channel

RESET

D7 D6 D5 D4 D3 D2 D1 D0 INT A2

A1 A0

Microprocessor Interface

SBP/IOM-2 Interface

09893H-1

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