AD9851FSPCB datasheet(8/24 Pages) AD

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AD9851

–8–

FREQUENCY OFFSET – Hz

–155

100

10k

100k

–145

–140

–135

–130

–125

–120

AD9851 RESIDUAL PHASE NOISE

–150

TPC 11. Output Residual Phase Noise (5.2 MHz AOUT), 6

OUT



REFCLK Multiplier Disabled, System Clock = 180 MHz, Ref-

erence Clock = 180 MHz

SYSTEM CLOCK FREQUENCY – MHz

100 120 140 160 180

VS = +3.3V

VS = +5V

FUNDAMENTAL OUTPUT =

SYSTEM CLOCK/3

TPC 12. Spurious-free dynamic range (SFDR) is generally

a function of the DAC analog output frequency. Analog

output frequencies of 1/3 the system clock rate are consid-

ered worst case. Plotted below are typical worst case SFDR

numbers for various system clock rates.

Ch1 100mV

T [ ]

Tek Stop 2.50GS/s

22 Acgs

 : 2.0ns

@ : 105.2ns

C1 Rise

2.03ns

M 20.0ns Ch 1

252mV

D 5.00ns Runs After

TPC 13. Comparator RiseTime, 15 pF Load

Ch1 100mV

T [

]

Tek Stop 2.50GS/s

2227 Acgs

 : 2.3ns

@ : 103.6ns

C1 Fall

2.33ns

M 20.0ns Ch 1

252mV

D 5.00ns Runs After

TPC 14. Comparator FallTime, 15 pF Load

ANALOG OUTPUT FREQUENCY – MHz

110

120

VS = +3.3V

VS = +5V

100

output frequency at 180 MHz system clock (upper

trace) and 125 MHz system clock (lower trace)

SYSTEM CLOCK – MHz

140

100

120

100

120

VS = +3.3V

VS = +5V

160

180

clock frequency

REV. D

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