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AD9549APCBZ bảng dữ liệu(PDF) 66 Page - Analog Devices |
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AD9549APCBZ bảng dữ liệu(HTML) 66 Page - Analog Devices |
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66 / 76 page  AD9549 Rev. D | Page 66 of 76 Register 0x030C—Control Table 81. Bits Bit Name Description 7 Enable REFA LOR The REFA LOR limits are set up in Registers 0x031E to Register 0x031F. 6 Enable REFA OOL The REFA OOL limits are set up in Register 0x0322 to Register 0x032B. 5 Enable REFB LOR The REFB LOR limits are set up in Register 0x0320 to Register 0x0321. 4 Enable REFB OOL The REFB OOL limits are set up in Register 0x032C to Register 0x0335. [3:2] Reserved Reserved. 1 Enable phase lock detector Register 0x0314 to Register 0x0318 must be set up to use this (see the Phase Lock Detection section). 0 Enable frequency lock detector Register 0x0319 must be set up to use this. See the Frequency Lock Detection section. Register 0x030D—Reserved Register 0x030E—HFTW (Read Only) Table 82. Bits Bit Name Description [7:0] Average or instantaneous FTW These read-only registers are the output of FTW monitor. Average or instantaneous is determined by holdover mode (see Bit 4, Register 0x01C0). These registers must be manually refreshed by issuing an I/O update. Register 0x030F—HFTW (Read Only) (Continued) Table 83. Bits Bit Name Description [15:8] Average or instantaneous FTW These read-only registers are the output of FTW monitor. Average or instantaneous is determined by holdover mode (see Bit 4, Register 0x01C0). These registers must be manually refreshed by issuing an I/O update. Register 0x0310—HFTW (Read Only) (Continued) Table 84. Bits Bit Name Description [23:16] Average or instantaneous FTW These read-only registers are the output of FTW monitor. Average or instantaneous is determined by holdover mode (see Bit 4, Register 0x01C0). These registers must be manually refreshed by issuing an I/O update. Register 0x0311—HFTW (Read Only) (Continued) Table 85. Bits Bit Name Description [31:24] Average or instantaneous FTW These read-only registers are the output of FTW monitor. Average or instantaneous is determined by holdover mode (see Bit 4, Register 0x01C0). These registers must be manually refreshed by issuing an I/O update. Register 0x0312—HFTW (Read Only) (Continued) Table 86. Bits Bit Name Description [39:32] Average or instantaneous FTW These read-only registers are the output of FTW monitor. Average or instantaneous is determined by holdover mode (see Bit 4, Register 0x01C0). These registers must be manually refreshed by issuing an I/O update. Register 0x0313—HFTW (Read Only) (Continued) Table 87. Bits Bit Name Description [47:40] Average or instantaneous FTW These read-only registers are the output of FTW monitor. Average or instantaneous is determined by holdover mode (see Bit 4, Register 0x01C0). These registers must be manually refreshed by issuing an I/O update. |
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