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AM28F010 bảng dữ liệu(PDF) 26 Page - Advanced Micro Devices |
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AM28F010 bảng dữ liệu(HTML) 26 Page - Advanced Micro Devices |
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26 / 35 page ![]() 26 Am28F010 SWITCHING TEST WAVEFORMS SWITCHING CHARACTERISTICS over operating range unless otherwise specified AC Characteristics—Read Only Operation Notes: 1. Guaranteed by design; not tested. 2. Not 100% tested. Parameter Symbols Am28F010 Speed Options JEDEC Standard Parameter Description -70 -90 -120 -150 -200 Unit tAVAV tRC Read Cycle Time (Note 2) Min 70 90 120 150 200 ns tELQV tCE Chip Enable AccessTime Max 70 90 120 150 200 ns tAVQV tACC Address Access Time Max 70 90 120 150 200 ns tGLQV tOE Output Enable Access Time Max 3535505555 ns tELQX tLZ Chip Enable to Output in Low Z (Note 2) Min 00000 ns tEHQZ tDF Chip Disable to Output in High Z (Note 1) Max 20 20 30 35 35 ns tGLQX tOLZ Output Enable to Output in Low Z (Note 2) Min 00000 ns tGHQZ tDF Output Disable to Output in High Z (Note 2) Max 20 20 30 35 35 ns tAXQX tOH Output Hold from first of Address, CE#, or OE# Change (Note 2) Min 00000 ns tWHGL Write Recovery Time before Read Min 66666 µs tVCS VCC Setup Time to Valid Read (Note 2) Min 50 50 50 50 50 µs 11559H-15 3 V 0 V Input Output 1.5 V 1.5 V Test Points AC Testing for -70 devices: Inputs are driven at 3.0 V for a logic “1” and 0 V for a logic “0”. Input pulse rise and fall times are ≤10 ns. 2.4 V 0.45 V Input Output Test Points 2.0 V 2.0 V 0.8 V 0.8 V AC Testing (all speed options except -70): Inputs are driven at 2.4 V for a logic “1” and 0.45 V for a logic “0”. Input pulse rise and fall times are ≤10 ns. |
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