AD7875LPZ1 datasheet(15/28 Pages) AD

15 / 28 page

AD7870/AD7875/AD7876

Rev. C | Page 15 of

CONVST

TRACK-AND-HOLD

GOES INTO HOLD

TRACK-AND-HOLD RETURNS

TO TRACK AND

ACQUISITION TIME BEGINS

THREE-STATE

VALID

DATA

DB11 TO DB0

INT

DATA

tCONVERT

Figure 14. Mode 1 Timing Diagram, 12-Bit Parallel Read

CONVST

INT

SSTRB2

DATA

SCLK3

TRACK-AND-HOLD RETURNS TO TRACK

AND ACQUISITION TIME BEGINS

TRACK-AND-HOLD GOES INTO HOLD

THREE-STATE

LEADING

ZEROS

VALID

DATA

DB7 TO DB0

VALID

DATA

DB11 TO DB8

HBEN1

SDATA2

1TIMES

t2, t3, t4, t8, AND t9 ARE THE SAME FOR A HIGH BYTE READ AS FOR A LOW BYTE READ.

2EXTERNAL 4.7kΩ PULL-UP RESISTOR.

3EXTERNAL 2kΩ PULL-UP RESISTOR;

CONTINUOUS SCLK (DASHED LINE) WHEN 12/8/CLK = –5V;

NONCONTINUOUS WHEN 12/8/CLK = 0V.

DB11

DB10

SERIAL DATA

DB0

tCONVERT

t11

t10

t12

t13

t14

Figure 15. Mode 1 Timing Diagram, Byte or Serial Read

The Mode 1 timing diagram for byte and serial data is shown

in Figure 15. INT goes low at the end of conversion and is reset

high by the first falling edge of CS and RD. This first read at the

end of conversion can either access the low byte or high byte of

data depending on the status of HBEN (

shows low

byte only for example). The diagram shows both a nonconti-

nuously and a continuously running clock (dashed line).

Figure 15

MODE 2 INTERFACE

The second interface mode is achieved by hard wiring

CONVST low and conversion is initiated by taking CS low

while HBEN is low. The track-and-hold amplifier goes into the

hold mode on the falling edge of CS. In this mode, the BUSY

/INT pin assumes its BUSY function. BUSY goes low at the start

of conversion, stays low during the conversion and returns high

when the conversion is complete. It is normally used in parallel

interfaces to drive the microprocessor into a WAIT state for the

duration of conversion. Mode 2 is not relevant for the AD7870A

device.

Figure 16 shows the Mode 2 timing diagram for the 12-bit

parallel data output format (12/8/CLK = +5 V). In this case, the

ADC behaves like slow memory. The major advantage of this

interface is that it allows the microprocessor to start conversion,

WAIT and then read data with a single READ instruction. The

user does not have to worry about servicing interrupts or

ensuring that software delays are long enough to avoid reading

during conversion.

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