FLEX8000 datasheet(13/62 Pages) ALTERA

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Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet

Internal Tri-State Emulation

Internal tri-state emulation provides internal tri-stating without the

limitations of a physical tri-state bus. In a physical tri-state bus, the

tri-state buffers’ output enable signals select the signal that drives the bus.

However, if multiple output enable signals are active, contending signals

can be driven onto the bus. Conversely, if no output enable signals are

active, the bus will float. Internal tri-state emulation resolves contending

tri-state buffers to a low value and floating buses to a high value, thereby

eliminating these problems. The MAX+PLUS II software automatically

implements tri-state bus functionality with a multiplexer.

Clear & Preset Logic Control

Logic for the programmable register’s clear and preset functions is

controlled by the DATA3, LABCTRL1, and LABCTRL2 inputs to the LE. The

clear and preset control structure of the LE is used to asynchronously load

signals into a register. The register can be set up so that LABCTRL1

implements an asynchronous load. The data to be loaded is driven to

DATA3

; when LABCTRL1 is asserted, DATA3 is loaded into the register.

During compilation, the MAX+PLUS II Compiler automatically selects

the best control signal implementation. Because the clear and preset

functions are active-low, the Compiler automatically assigns a logic high

to an unused clear or preset.

The clear and preset logic is implemented in one of the following six

asynchronous modes, which are chosen during design entry. LPM

functions that use registers will automatically use the correct

asynchronous mode. See Figure 7.

■

Clear only

■

Preset only

■

Clear and preset

■

Load with clear

■

Load with preset

■

Load without clear or preset

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