AD7862

–9–

REV. 0

and fourth read pulses, after the second conversion and A0 high,

state can be changed any time after the CONVST goes high,

i.e., track/holds into hold, and 400 ns prior to the next falling

edge of CONVST. Data is read from the part via a 12-bit

parallel data bus with standard CS and RD signal, i.e., the read

operation consists of a negative going pulse on the CS pin

combined with two negative going pulses on the RD pin (while

the CS is low), accessing the two 12-bit results. Once the read

operation has taken place, a further 300 ns should be allowed

before the next falling edge of CONVST to optimize the settling

of the track/hold amplifier before the next conversion is initiated.

With the internal clock frequency at its maximum (3.7 MHz—not

accessible externally), the achievable throughput rate for the

part is 3.6

µs (conversion time) plus 100 ns (read time) plus

0.3

µs (acquisition time). This results in a minimum throughput

time of 4

µs (equivalent to a throughput rate of 250 kHz).

Read Options

Apart from the read operation described above and displayed in

Figure 5a, other CS and RD combinations can result in

different channels/inputs being read in different combinations.

Suitable combinations are shown in Figures 5b through 5d.

CS

RD

DATA

Figure 5b. Read Option A

CS

RD

DATA

Figure 5c. Read Option B

A0

CS

RD

DATA

Figure 5d. Read Option C

OPERATING MODES

Mode 1 Operation (High Sampling Performance)

The timing diagram in Figure 5a is for optimum performance in

operating mode 1 where the falling edge of CONVST starts

conversion and puts the track/hold amplifiers into their hold

mode. This falling edge of CONVST also causes the BUSY

signal to go high to indicate that a conversion is taking place.

The BUSY signal goes low when the conversion is complete,

which is 3.6

µs max after the falling edge of CONVST, and new

data from this conversion is available in the output latch of the

AD7862. A read operation accesses this data. If the multiplexer

select A0 is low, the first and second read pulses after the first

t

3

t

1

t

2

t

4

t

5

t

6

t

CONVST

BUSY

A0

CS

RD

DATA

300ns

400ns

Figure 5a. Mode 1 Timing Operation Diagram for High Sampling Performance