AD7225LPZ datasheet(15/24 Pages) AD

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AD7225

Rev. C | Page 15 of 24

AGND BIAS

The AD7225 AGND pin can be biased above system ground

(AD7225 DGND) to provide an offset zero analog output

voltage level. Figure 18 shows a circuit configuration to achieve

this for DAC Channel A of the AD7225. The output voltage,

VOUTA, can be expressed as:

VOUTA = VBIAS + DA(VIN)

where DA is a fractional representation of the digital word in

DAC Latch A (0 ≤ DA ≤ 255/256).

VDD

VSS

AGND

VBIAS

VIN

DGND

VOUTA

DAC A

AD7225*

VREFA

*DIGITAL INPUTS OMITTED FOR CLARITY.

Figure 18. AGND Bias Circuit

For a given VIN, increasing AGND above system ground reduces

the effective VDD − VREF, which must be at least 4 V to ensure

specified operation. Note that, because the AGND pin is

common to all four DACs, this method biases up the output

voltages of all the DACs in the AD7225. Note that VDD and VSS

of the AD7225 should be referenced to DGND.

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