GAL16V8D-25LS datasheet(19/26 Pages) LATTICE

19 / 26 page

Specifications GAL16V8

Typ. Vref = 3.2V

Typical Output

Typ. Vref = 3.2V

Typical Input

INPUT/OUTPUT EQUIVALENT SCHEMATICS

Circuitry within the GAL16V8 provides a reset signal to all reg-

isters during power-up. All internal registers will have their Q

outputs set low after a specified time (

tpr, 1μs MAX). As a result,

the state on the registered output pins (if they are enabled) will

always be high on power-up, regardless of the programmed

polarity of the output pins. This feature can greatly simplify state

machine design by providing a known state on power-up. Be-

cause of the asynchronous nature of system power-up, some

Vcc

Vref

Active Pull-up

Circuit

ESD

Protection

Circuit

ESD

Protection

Circuit

Vcc

Vref

Tri-State

Control

Active Pull-up

Circuit

Feedback

(To Input Buffer)

Feedback

Data

Output

Vcc

CLK

INTERNAL REGISTER

Q - OUTPUT

FEEDBACK/EXTERNAL

OUTPUT REGISTER

Vcc (min.)

tpr

Internal Register

Reset to Logic "0"

Device Pin

Reset to Logic "1"

twl

tsu

conditions must be met to provide a valid power-up reset of the

device. First, the VCC rise must be monotonic. Second, the clock

input must be at static TTL level as shown in the diagram during

power up. The registers will reset within a maximum of

tpr time.

As in normal system operation, avoid clocking the device until all

input and feedback path setup times have been met. The clock

must also meet the minimum pulse width requirements.

Power-Up Reset

Input/Output Equivalent Schematics

GAL16V8D-25LS bảng dữ liệu(PDF) 19 Page - Lattice Semiconductor

GAL16V8D-25LS bảng dữ liệu(HTML) 19 Page - Lattice Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

bảng dữ liệu tải về

Link URL