AX2000 datasheet(117/262 Pages) MICROSEMI

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Axcelerator Family FPGAs

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Table 2-99 • Two FIFO Blocks Cascaded

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70°C

–2 Speed

–1 Speed

Std Speed

Units

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

FIFO Module Timing

tWSU

Write Setup

13.75

15.66

18.41

tWHD

Write Hold

0.00

tWCKH

WCLK High

0.75

tWCKL

WCLK Low

1.76

tWCKP

Minimum WCLK Period

2.51

tRSU

Read Setup

14.33

16.32

19.19

tRHD

Read Hold

0.00

tRCKH

RCLK High

0.73

tRCKL

RCLK Low

1.89

tRCKP

Minimum RCLK period

2.62

tCLRHF

Clear High

0.00

tCLR2FF

Clear-to-flag (EMPTY/FULL)

1.92

2.18

2.57

tCLR2AF

Clear-to-flag (AEMPTY/AFULL)

4.39

5.00

5.88

tCK2FF

Clock-to-flag (EMPTY/FULL)

2.13

2.42

2.85

tCK2AF

Clock-to-flag (AEMPTY/AFULL)

5.04

5.75

6.75

tRCK2RD1

RCLK-To-OUT (Pipelined)

1.43

1.63

1.92

tRCK2RD2

RCLK-To-OUT (Nonpipelined)

2.26

2.58

3.03

Note:

Timing data for these two cascaded FIFO blocks uses a depth of 8,192. For all other combinations, use

Microsemi’s timing software.

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