AX2000 datasheet(111/262 Pages) MICROSEMI

111 / 262 page

Axcelerator Family FPGAs

Re vi s i on 18

2 - 97

Figure 2-63 illustrates flag generation.

The Verilog codes for the flags are:

assign AF = (DIFF[15:0] >={AFVAL[7:0],8'b00000000})?1:0;

assign AE = ({AEVAL[7:0],8'b00000000}>=DIFF[15:0])?1:0;

The number of DIFF-bits active depends on the configuration depth and width (Table 2-95).

The active-high CLR pin is used to reset the FIFO to the empty state, which sets FULL and AFULL low,

and EMPTY and AEMPTY high.

Assuming that the EMPTY flag is not set, new data is read from the FIFO when REN is valid on the active

edge of the clock. Write and read transfers are described with timing requirements in "Timing

Characteristics" on page 2-100.

Figure 2-63 • ALMOST-EMPTY and ALMOST-FULL Logic

Table 2-95 • Number of Available Configuration Bits

Number of Blocks

Block DxW

Number of AEVAL/AFVAL Bits

1x1

1x2

2x1

1x4

2x2

4x1

1x8

2x4

4x2

8x1

1x16

2x8

4x4

8x2

16x1

ALMOST EMPTY and ALMOST FULL Logic

WCNTR

[15:0]

WCLK

RCNTR

[15:0]

RCLK

AEMPTY

AFULL

X>=Y

(16 bit)

DIFF [15:0]

AEVAL [7:0], GND [7:0] (MSB....LSB)

AFVAL [7:0], GND [7:0] (MSB....LSB)

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