MCP9803 datasheet(17/30 Pages) MICROCHIP

17 / 30 page

 2004 Microchip Technology Inc.

DS21909B-page 17

MCP9800/1/2/3

5.1.5

DATA VALID

After the start condition, each bit of data in transmission

needs to be settled for time specified by tSU-DATA

before SCLK toggles from low-to-high (refer to the

Serial Interface Timing Specification).

5.1.6

ACKNOWLEDGE (ACK)

Each receiving device, when addressed, is obliged to

generate an acknowledge bit after the reception of

each byte. The master device must generate an extra

clock pulse for ACK to be recognized.

The acknowledging device has to pull down the SDA

line for tSU-DATA before the low-to-high transition of

SCLK from the Master and remains pulled down for

tH-DATA after high-to-low transition of SCLK.

During read, the master must signal an End-of-Data

(EOD) to the slave by not generating an ACK bit once

the last bit has been clocked out of the slave. In this

case, the slave will leave the data line released to

enable the master to generate the stop condition.

5.1.7

TIME OUT (MCP9802/03)

If the SCLK stays low for time specified by tOUT, the

MCP9802/03 resets the serial interface. This dictates

the minimum clock speed as specified in the SMBus

specification. The I2C bus specification does not limit

clock speed and, therefore, the master can hold the

clock indefinitely to process data (MCP9800/01 only).

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