MP8762GL datasheet(36/39 Pages) MPS

36 / 39 page

MP8762 ― 10A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER

MP8762 Rev. 1.4

www.MonolithicPower.com

11/4/2013

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

LAYOUT RECOMMENDATION

1. MPS offers two packages, but recommends

MP8762GLE with its 16-pin QFN package for

all new designs due to its smaller parasitical

inductance.

2. Place high current paths (GND, IN, and SW)

very close to the device with short, direct and

wide traces.

3. The 13-pin QFN package requires two copper

layers

for

better

performance.

Respectively put at least a decoupling

capacitor on both Top and Bottom layers and

as close to the IN and GND pins as possible.

Also, several vias with 18mil diameter and

8mil hole- size are required to be placed

under the device and near input capacitors to

help on the thermal dissipation, also reduce

the parasitic inductance.

4. Put a decoupling capacitor as close to the

VCC and AGND pins as possible.

5. Keep the switching node (SW) plane as small

as possible and far away from the feedback

network.

6. Place the external feedback resistors next to

the FB pin. Make sure that there are no vias

on the FB trace. The feedback resistors

should refer to AGND instead of PGND.

7. Keep the BST voltage path (BST, C3, and

SW) as short as possible.

8. Recommend strongly a four-layer layout to

improve thermal performance.

MP8762

Figure 55—Schematic For PCB Layout Guide

VIN

GND

VOUT

PGND

GND

Top Layer

GND

Inner1 Layer

GND

Inner2 Layer

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