PIC18F4550ESPQTP datasheet(47/438 Pages) MICROCHIP

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DS39632E-page 45

PIC18F2455/2550/4455/4550

4.0

RESET

The PIC18F2455/2550/4455/4550 devices differentiate

between various kinds of Reset:

Power-on Reset (POR)

MCLR Reset during normal operation

MCLR Reset during power-managed modes

Watchdog Timer (WDT) Reset (during

execution)

Programmable Brown-out Reset (BOR)

RESET Instruction

Stack Full Reset

Stack Underflow Reset

This section discusses Resets generated by MCLR,

POR and BOR and covers the operation of the various

start-up timers. Stack Reset events are covered in

Section 5.1.2.4 “Stack Full and Underflow Resets”.

WDT Resets are covered in Section 25.2 “Watchdog

Timer (WDT)”.

A simplified block diagram of the on-chip Reset circuit

is shown in Figure 4-1.

4.1

RCON Register

Device Reset events are tracked through the RCON

ter indicate that a specific Reset event has occurred. In

most cases, these bits can only be cleared by the event

and must be set by the application after the event. The

state of these flag bits, taken together, can be read to

indicate the type of Reset that just occurred. This is

described in more detail in Section 4.6 “Reset State

of Registers”.

The RCON register also has control bits for setting

interrupt priority (IPEN) and software control of the

BOR (SBOREN). Interrupt priority is discussed in

Section 9.0 “Interrupts”.

BOR

is covered

Section 4.4 “Brown-out Reset (BOR)”.

FIGURE 4-1:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External Reset

MCLR

VDD

OSC1

WDT

Time-out

VDD Rise

Detect

OST/PWRT

INTRC(1)

POR Pulse

OST

10-Bit Ripple Counter

PWRT

Chip_Reset

11-Bit Ripple Counter

Enable OST(2)

Enable PWRT

Note 1: This is the low-frequency INTRC source from the internal oscillator block.

2: See Table 4-2 for time-out situations.

Brown-out

Reset

BOREN

RESET

Instruction

Stack

Pointer

Stack Full/Underflow Reset

Sleep

( )_IDLE

1024 Cycles

65.5 ms

μs

MCLRE

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