MP1492 – 2A, 4.2V-16V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER

MP1492 Rev. 1.1

www.MonolithicPower.com

10

3/13/2012

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© 2012 MPS. All Rights Reserved.

HS-FET deviates from its intended location and

produces jitter. It is necessary to understand that

there is a relationship between a system’s

ripple

dominates

in

noise

immunity.

The

the noise immunity directly.

Figure 3—Jitter in PWM Mode

Figure 4—Jitter in Skip Mode

Ramp with Large ESR Cap

In the case of POSCAP or other types of

capacitor with larger ESR is applied as output

capacitor. The ESR ripple dominates the output

ripple, and the slope on the FB is quite ESR

related. Figure 5 shows an equivalent circuit in

PWM mode with the HS-FET off and without an

external ramp circuit. Turn to application

information section for design steps with large

ESR caps.

R1

R2

ESR

POSCAP

SW

FB

Vo

L

Figure 5—Simplified Circuit in PWM Mode

without External Ramp Compensation

To realize the stability when no external ramp is

used, usually the ESR value should be chosen

as follow:

SW

ON

ESR

OUT

TT

0.7

2

R

C

+

×π

≥

(3)

Ramp with small ESR Cap

When the output capacitors are ceramic ones,

the ESR ripple is not high enough to stabilize the

system, and external ramp compensation is

needed. Skip to application information section

for design steps with small ESR caps.

R1

R2

Ceramic

SW

FB

Vo

L

R4

C4

R9

Figure 6—Simplified Circuit in PWM Mode

with External Ramp Compensation

In PWM mode, an equivalent circuit with HS-FET

off

and

the

use

of

an

external

ramp

compensation circuit (R4, C4) is simplified in

Figure 6. The external ramp is derived from the

inductor ripple current. If one chooses C4, R9,

R1 and R2 to meet the following condition:

12

9

SW

4

1

2

RR

11

R

2F

C

5

R

R

⎛⎞

×

<×

+

⎜⎟

π×

×

+

⎝⎠

(4)

Where:

R4

C4

FB

C4

II

II

=

+≈

(5)

as:

IN

O

12

RAMP

ON

44

1

2

9

VV

R//R

VT

RC

R // R

R

−

=×

×

×+

(6)

follows