LMP91050

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SNAS517D – NOVEMBER 2011 – REVISED MARCH 2013

Bit

Bit Symbol

Description

00: PGA1 OFF PGA2 OFF (default)

01: PGA1 OFF, PGA2 ON

[6:5]

EN

10: PGA1 ON, PGA2 OFF

11: PGA1 ON, PGA2 ON

0: PGA1 to PGA2 direct (default)

4

EXT_FILT

1: PGA1 to PGA2 via external filter

0 : 1.15V (default)

3

CMN_MODE

1 : 2.59V

00: 4 (default)

01: 8

[2:1]

GAIN2

10: 16

11: 32

0: 250 (default)

0

GAIN1

1: 42

DAC Configuration – DAC Configuration Register (Address 0x1)

The output DC level will shift according to the formula Vout_shift = -33.8mV * (NDAC - 128).

Bit

Bit Symbol

Description

[7:0]

NDAC

128 (0x80): Vout_shift = -33.8mV * (128 - 128) = 0mV (default)

SDIO Mode – SDIO Mode Enable Register (Address 0xf)

Write-only

Bit

Bit Symbol

Description

To enter SDIO Mode, write the successive sequence 0xFE and 0xED.

[7:0]

SDIO_MODE_EN

Write anything other than this sequence to get out of mode.

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