High-Speed Interconnect

Program/Data Storage

Connectivity

Display Subsystem

System

(2x ARM®

Cortex™–A15)

IVA HD

1080p Video

Co-Processor

DSP

(2x C66x™

Co-Processors)

PCIe

GMAC AVB

Up to 2.5 MB

RAM w/ ECC

(NAND/NOR/

Async)

(2x SGX544 3D)

3x VIP

4x EVE Analytic Processors

(2x Cortex™–M4)

intro-001

GPMC / ELM

256KB ROM

OCMC

TDA2x Superset

GPU

MPU

IPU

Serial Interfaces

I2C x5

UART x10

McSPI x4

DCAN x2

Spinlock

Mailbox x13

GPIO x8

Timers x16

WDT

QSPI

LCD1

Overlay

1x GFX Pipeline

3x Video Pipelines

HDMI 1.4a

EMIF x2

2x 32b

DDR2/3 w/ ECC

JTAG

PLLs

OSC

PRU SS

EDMA

VPE

DMM

McASP

2x MMU

Vision AccelerationPac

TDA2

www.ti.com

SPRT680 – OCTOBER 2013

1.4

Functional Block Diagram

Figure 1-1 is functional block diagram of the superset.

Figure 1-1. TDA2x Superset Block Diagram

Copyright © 2013, Texas Instruments Incorporated

Advanced Driver Assistance System (ADAS) TDA2x System-on-Chip

3

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