PIC18F2680ISPQTP datasheet(444/482 Pages) MICROCHIP

444 / 482 page

PIC18F2585/2680/4585/4680

DS39625C-page 442

Preliminary

FIGURE 27-14:

EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)

TABLE 27-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)

Param

No.

Symbol

Characteristic

Min

Max Units Conditions

TSSL2SCH,

TSSL2SCL

↓ to SCK ↓ or SCK ↑ Input

TCY

—ns

TSCH

SCK Input High Time

Continuous

1.25 TCY + 30

—

71A

Single Byte

—

(Note 1)

TSCL

SCK Input Low Time

Continuous

1.25 TCY + 30

—

72A

Single Byte

—

(Note 1)

TDIV2SCH,

TDIV2SCL

Setup Time of SDI Data Input to SCK Edge

100

—

73A

TB2B

Last Clock Edge of Byte1 to the First Clock Edge of Byte 2 1.5 TCY + 40

—

(Note 2)

TSCH2DIL,

TSCL2DIL

Hold Time of SDI Data Input to SCK Edge

100

—

TDOR

SDO Data Output Rise Time

PIC18FXXXX

—

PIC18LFXXXX

VDD = 2.0V

TDOF

SDO Data Output Fall Time

—

TSSH2DOZSS

↑ to SDO Output High-Impedance

TSCH2DOV,

TSCL2DOV

SDO Data Output Valid after SCK Edge PIC18FXXXX

—

PIC18LFXXXX

100

VDD = 2.0V

TscH2ssH,

TscL2ssH

↑ after SCK Edge

1.5 TCY + 40

—

Note 1:

Requires the use of Parameter #73A.

Only if Parameter #71A and #72A are used.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

75, 76

SDI

MSb

LSb

bit 6 - - - - - -1

MSb In

bit 6 - - - -1

LSb In

Note:

Refer to Figure 27-4 for load conditions.

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