PIC18F2680ISPQTP datasheet(399/482 Pages) MICROCHIP

399 / 482 page

Preliminary

DS39625C-page 397

PIC18F2585/2680/4585/4680

SUBLW

Subtract W from Literal

Syntax:

SUBLW k

Operands:

≤ k ≤ 255

Operation:

k – (W)

→ W

Status Affected:

N, OV, C, DC, Z

Encoding:

0000

1000

kkkk

Description:

W is subtracted from the eight-bit

literal ‘k’. The result is placed in W.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

literal ‘k’

Process

Data

Write to W

Example 1:

SUBLW

02h

Before Instruction

01h

After Instruction

01h

; result is positive

Example 2:

SUBLW

02h

Before Instruction

02h

After Instruction

00h

; result is zero

Example 3:

SUBLW

02h

Before Instruction

03h

After Instruction

FFh; (2’s complement)

; result is negative

SUBWF

Subtract W from f

Syntax:

SUBWF

f {,d {,a}}

Operands:

≤ f ≤ 255

∈ [0,1]

Operation:

(f) – (W)

→ dest

Status Affected:

N, OV, C, DC, Z

Encoding:

0101

11da

ffff

Description:

Subtract W from register ‘f’ (2’s

complement method). If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’

(default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f

≤ 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write to

destination

Example 1:

SUBWF

REG, 1, 0

Before Instruction

REG

After Instruction

REG

; result is positive

Example 2:

SUBWF

REG, 0, 0

Before Instruction

REG

After Instruction

REG

; result is zero

Example 3:

SUBWF

REG, 1, 0

Before Instruction

REG

After Instruction

REG

FFh ;(2’s complement)

; result is negative

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