S25FS-S datasheet(25/154 Pages) SPANSION

25 / 154 page

November 6, 2013 S25FS-S_00_04

S25FS-S Family

Da ta

Shee t

(Prelim i nar y )

 The address or mode bits may be followed by write data to be stored in the memory device or by a read

latency period before read data is returned to the host.

 Write data bit transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR

commands.

 SCK continues to toggle during any read access latency period. The latency may be zero to several SCK

cycles (also referred to as dummy cycles). At the end of the read latency cycles, the first read data bits are

driven from the outputs on SCK falling edge at the end of the last read latency cycle. The first read data

bits are considered transferred to the host on the following SCK rising edge. Each following transfer occurs

on the next SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.

 If the command returns read data to the host, the device continues sending data transfers until the host

takes the CS# signal high. The CS# signal can be driven high after any transfer in the read data sequence.

This will terminate the command.

 At the end of a command that does not return data, the host drives the CS# input high. The CS# signal

must go high after the eighth bit, of a stand alone instruction or, of the last write data byte that is

transferred. That is, the CS# signal must be driven high when the number of bits after the CS# signal was

driven low is an exact multiple of eight bits. If the CS# signal does not go high exactly at the eight bit

boundary of the instruction or write data, the command is rejected and not executed.

 All instruction, address, and mode bits are shifted into the device with the Most Significant Bits (MSB) first.

The data bits are shifted in and out of the device MSB first. All data is transferred in byte units with the

lowest address byte sent first. The following bytes of data are sent in lowest to highest byte address order

i.e. the byte address increments.

 All attempts to read the flash memory array during a program, erase, or a write cycle (embedded

operations) are ignored. The embedded operation will continue to execute without any affect. A very

limited set of commands are accepted during an embedded operation. These are discussed in the

individual command descriptions.

 Depending on the command, the time for execution varies. A command to read status information from an

executing command is available to determine when the command completes execution and whether the

command was successful.

4.2.1

Command Sequence Examples

Figure 4.3 Stand Alone Instruction Command

Figure 4.4 Single Bit Wide Input Command

CS#

SCLK

Phase

Instruction

CS#

SCLK

Phase

Instruction

Input Data

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