TAS5706APAPR datasheet(13/71 Pages) TI1

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2C SERIAL CONTROL PORT OPERATION

SCL

SDA

w(H)

w(L)

su1

T0027-01

SCL

SDA

(buf)

su2

su3

Start

Condition

Stop

Condition

T0028-01

TAS5706A

TAS5706B

www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009

Timing characteristics for I

2C Interface signals over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

fSCL

Frequency, SCL

No wait states

400

kHz

tw(H)

Pulse duration, SCL high

0.6

µs

tw(L)

Pulse duration, SCL low

1.3

µs

Rise time, SCL and SDA

300

Fall time, SCL and SDA

300

tsu1

Setup time, SDA to SCL

100

th1

Hold time, SCL to SDA

t(buf)

Bus free time between stop and start condition

1.3

µs

tsu2

Setup time, SCL to start condition

0.6

µs

th2

Hold time, start condition to SCL

0.6

µs

tsu3

Setup time, SCL to stop condition

0.6

µs

Load capacitance for each bus line

400

Figure 2. SCL and SDA Timing

Figure 3. Start and Stop Conditions Timing

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Product Folder Link(s): TAS5706A TAS5706B

TAS5706A is Not Recommended for New Designs

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