Product Specification

PE9701

Page 6 of 13

©2003-2006 Peregrine Semiconductor Corp. All rights reserved.

Document No. 70-0035-02

│ UltraCMOS™ RFIC Solutions

Note 1:

Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk

specification.

Note 2:

Note 3:

Parameter is guaranteed through characterization only, and is not tested.

Symbol

Parameter

Conditions

Min

Max

Units

Control Interface and Latches (see Figures 4, 5, 6)

Serial data clock frequency

(Note 1)

10

MHz

Serial clock HIGH time

30

ns

Serial clock LOW time

30

ns

Sdata hold time after Sclk rising edge, D[7:0] set-up time to

M1_WR, M2_WR, A_WR, E_WR rising edge

10

ns

Sdata hold time after Sclk rising edge, D[7:0] hold time to

M1_WR, M2_WR, A_WR, E_WR rising edge

10

ns

S_WR, M1_WR, M2_WR, A_WR, E_WR pulse width

30

ns

Sclk rising edge to S_WR rising edge. S_WR, M1_WR,

M2_WR, A_WR falling edge to Hop_WR rising edge

30

ns

Sclk falling edge to E_WR transition

30

ns

S_WR falling edge to Sclk rising edge. Hop_WR falling

edge to S_WR, M1_WR, M2_WR, A_WR rising edge

30

ns

E_WR transition to Sclk rising edge

30

ns

MSEL data out delay after Fin rising edge

8

ns

Main Divider (Prescaler Enabled)

Operating frequency

500

3000

MHz

Input level range

External AC coupling

-5

5

dBm

Main Divider (Prescaler Bypassed)

Operating frequency

50

300

MHz

Input level range

External AC coupling

-5

5

dBm

Reference Divider

Operating frequency

(Note 3)

100

MHz

Reference input power (Note 2)

Single-ended input

-2

dBm

Phase Detector

Comparison frequency

(Note 3)

20

MHz