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DP83840AVCE bảng dữ liệu(PDF) 13 Page - Texas Instruments

tên linh kiện DP83840AVCE
Giải thích chi tiết về linh kiện  10/100 Mb/s Ethernet Physical Layer
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DP83840AVCE bảng dữ liệu(HTML) 13 Page - Texas Instruments

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2.0 Pin Description (Continued)
12
National Semiconductor
Version A
2.7 IEEE 1149.1 INTERFACE
The IEEE 1149.1 Standard Test Access Port and Boundary Scan (sometimes referred to as JTAG) interface signals
allow system level boundary scan to be performed. These pins may be left floating when JTAG testing is not required.
Signal Name
Type
Pin #
Description
TDO
O, Z
50
TEST DATA OUTPUT: Serial instruction/test output data for the IEEE 1149.1
scan chain.
If Boundary-Scan is not implemented this pin may be left unconnected (NC).
TDI
I
91
TEST DATA INPUT: Serial instruction/test input data for the IEEE 1149.1 scan
chain.
TRST
I
92
TEST RESET: An asynchronous low going pulse will reset and initialize the IEEE
1149.1 test circuitry.
If Boundary-Scan is not implemented, this pin may be left unconnected (NC) since
it has an internal pull-up resistor (10 k
Ω).
TCLK
I
93
TEST CLOCK: Test clock for the IEEE 1149.1 circuitry.
If Boundary-Scan is not implemented this pin may be left unconnected (NC).
TMS
I
94
TEST MODE SELECT: Control input to the IEEE 1149.1 test circuitry.
If Boundary-Scan is not implemented, this pin may be left unconnected (NC) since
it has an internal pull-up resistor (10 k
Ω).
I = TTL/CMOS input
O = TTL/CMOS output
Z = TRI-STATE output
J = IEEE 1149.1 pin



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