APW8813 datasheet(21/31 Pages) ANPEC

21 / 31 page

Rev. A.6 - Sep., 2012

APW8813/A

www.anpec.com.tw

Function Description (Cont.)

PWM Converter Current-Limit

The current-limit circuit employs an unique “valley” cur-

rent sensing algorithm (Figure 2). CS pin should be con-

nected to VCC through the trip voltage-setting resistor,

CS. CS terminal sinks 10µA current, ICS, and the current-

limit threshold is set to the voltage across the R

CS. The

voltage between PGND and PHASE pin monitors the in-

ductor current so that PHASE pin should be connected to

the drain terminal of the low side MOSFET. PGND is used

as the positive current sensing node so that PGND

should be connected to the proper current sensing device,

i.e. the sense resistor or the source terminal of the low

side MOSFET.

If the magnitude of the current-sense signal is above the

current-limit threshold, the PWM is not allowed to initiate

a new cycle. The actual peak current is greater than the

current-limit threshold by an amount equal to the induc-

tor ripple current. Therefore, the exact current-limit char-

acteristic and maximum load capability are the function

of the sense resistance, inductor value, and input voltage.

The equation for the current-limit threshold is as below:

Where

LIMIT is the desired current-limit threshold

CS is the value of the current sense resistor con-

nected to CS and VCC pins

CS is the voltage across the RCS resistor

RIPPLE is inductor peak to peak current

SW is the PWM switching frequency

In a current-limit condition, the current to the load exceeds

the current to the output capacitor, thus the output voltage

tends to fall down. If the output voltage becomes less

than power good level, the V

CS is cut into half and the

output voltage tends to be even lower. Eventually, it

crosses the under-voltage protection threshold and

shutdown.

(

)

VDDQ

DS(ON)

RIPPLE

DS(ON)

LIMIT

−

Time

LIMIT

PEAK

VALLEY

Figure 2. Current-Limit Algorithm

VTT Sink/Source Regulator

The output voltage at VTT pin tracks the reference voltage

applied at VTTREF pin. Two internal N-channel MOSFETs

controlled by separate high bandwidth error amplifiers

regulate the output voltage by sourcing current from LDOIN

pin or sinking current to GND pin. To prevent two pass

transistors from shoot-through, a small voltage offset is

created between the positive inputs of the two error

amplifiers. The VTT with fast response feedback loop

keeps tracking to the VTTREF within ±40mV at all condi-

tions including fast load transient.

S3, S5 Control

In the DDR2/DDR3 memory applications, it is important

to keep VDDQ always higher than VTT/VTTREF including

both start-up and shutdown.

The S3 and S5 signals control the VDDQ, VTT, VTTREF

states and these pins should be connected to SLP_S3

and SLP_S5 signals respectively. The table1 shows the

truth table of the S3 and S5 pins. When both S3 and S5

are above the logic threshold voltage, the VDDQ, VTT and

VTTREF are turned on at S0 state. When S3 is low and

S5 is high, the VDDQ and VTTREF are kept on while the

VTT voltage is disabled and left high impedance in S3

state. When both S3 and S5 are low, the VDDQ, VTT and

VTTREF are turned off and discharged to the ground ac-

cording to the discharge mode selected by MODE pin

during S4/S5 state, only for APW8813. On APW8813A, the

default discharge mode is non-tracking discharge.

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