APW8812 datasheet(13/24 Pages) ANPEC

13 / 24 page

Rev. A.2 - Sep., 2012

APW8812

www.anpec.com.tw

Reference Voltages and Linear Regulator

(REF and LDO3/5)

The 2V reference, REF, is accurate to ±1% over-

temperature. Bypass to GND with a 0.1

µF (minimum)

capacitor. REF can source up to 50

µA for external loads.

However, avoid loading REF if extremely accurate speci-

fications for both the main output voltages and REF are

essential. In addition, REF voltage must be bigger than

its rising enable threshold, and then the LDO output starts

to rise up.

The LDO3 and LDO5 regulators can supply up to 100mA

for external loads. Bypass to GND with a minimum of

2.2

µF ceramic capacitor for stability. When ENLDO is

enabled, the V

LDO3 is fixed 3.33V and the VLDO5 is fixed 5V in

standby mode. When PWMx output voltage is over whose

bypass threshold(PWM1 is 4.7V and PWM2 is 3.15V), the

switchover between the internal LDOx and VOUTx is

workable. These actions change the current path to power

the loads from the PWMx regulateon voltage, rather than

from the internal linear regulator.

Function Description (Cont.)

Ultrasonic Mode (Cont.)

A Power-On-Reset (POR) function is designed to prevent

wrong logic controls. The POR function continually moni-

tors the supply voltage on the LDO5 pins. LDO5 POR

circuitry inhibits wrong switching. When the rising V

LDO5

voltage reaches the rising POR threshold (4.2V typ.), the

output voltages begin to ramp up. When the LDO5 volt-

age is lower than 4.1V(typ.) or LDO3 voltage is lower than

2.5V(typ.), both switch power supplies are shut off. This

is non-latch protection. LDO5 POR threshold could reset

the under-voltage, over-voltage.

Power-On-Reset

The APW8812 integrates digital soft-start circuit to ramp

up the PWMx output voltage of the converter to the pro-

grammed regulation set point at a predictable slew rate.

The slew rate of PWMx output voltage is internally con-

trolled to limit the inrush current through the output ca-

pacitors during soft-start process. When the ENILIMx pin

is pulled above the rising threshold voltage, the related

PWM initiates a soft-start process to ramp up the output

voltage. The soft-start interval is 1.7ms(typ.) and inde-

pendent of the UGATE switching frequency.

Digital Soft-Start

The APW8812 has two independent enable controls for

PWM and LDO. When the ENLDO pin is higher than 0.8V,

the REF, LDO3 and LDO5 are enabled to standby mode.

It means that the PWM1 and PWM2 are ready to enable at

this mode. When the ENPWM pin is high (ENILIMx=1) at

standby mode, the PWMx initiates a soft-start process to

ramp up the output voltage. The PWM1 and PWM2 are

controlled individually by ENILIM1 and ENILIM2. When

ENLDO, ENILIM1 and ENILIM2 are low, the chip is in its

low-power shutdown state. The APW8812 only consumes

µA of quiescent current while in shutdown. When the

ENLDO is higher than 2.4V and ENILIM1 is high

(ENILIM1=1), the clock signal becomes available from

VCLK pin. Both PWM outputs are discharged to 0V

through a 25

Ω switch and both LDO outputs are dis-

charged to 0V through a 40W switch in shutdown mode.

Driving ENILIM1 and ENILIM2 (logic AND) or ENLDO be-

low 0.4V clears the over-voltage, under-voltage and over-

temperature fault latches.

Enable Controls

The condition for the 270kHz clock signal to be used is

that the ENLDO is higher than 2.4V and ENILIM1 is high

(ENILIM1=1). When VOUT1 regulates at 5V and the clock

signal uses VOUT1 as its power supply, the charge pump

circuit can generate approximately 15V DC voltage. The

example of charge pump circuit is shown in typical appli-

cation circuit.

Charge Pump

controller turns off the low-side MOSFET and triggers a

constant-on-time. When the constant-on-time has

expired, the controller turns on the low-side MOSFET

again until the inductor current is below the zero-cross-

ing threshold. The behavior is the same with PFM mode.

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